Abhishek Khanna

Bio

Abhishek Khanna completed his B.Tech and Masters in Electrical Engineering from IIT Bombay in Mumbai, India. Since 2017 he has been a PhD student at Notre Dame focused on experimental demonstrations of analog computing with non-CMOS hardware, along with device fabrication and characterization of complex correlated oxides. He is currently working towards creating coupled phase-transition nano-oscillator based systems to solve combinatorial optimization problems. He has also demonstrated ferroelectric FET based ternary content addressable memory arrays, as well as developed high temperature Lanthanum Cobaltite based vertical selectors for emerging crossbar memories. He has previously been a Visiting Research Scholar to IBM Research, Zurich and has won the Best Poster Award at IEEE/CAS AI Compute Symposium 2019 held at IBM T.J. Watson Research Lab, New York. 

Selected Publications

1. S. Dutta*, A. Khanna*, et. al ‘An Ising Hamiltonian solver based on coupled stochastic phase-transition nano-oscillators’
Nature Electronics, July 2021
2. A. Khanna*, S. Dutta* et. al ‘Lifelong Learning with Monolithic 3D Ferroelectric Ternary Content-Addressable Memory’
2021 International Electron Device Meeting 
3. E. Corti, A. Khanna, et. al ‘Time-Delay Encoded Image Recognition in a Network of Resistively Coupled VO2 on Si Oscillators’
IEEE Electron Device Letters, Feb 2020
4. G. Detorakis, S. Dutta, A. Khanna, et. al ‘Inherent weight normalization in stochastic neural networks’ 
2019 Advances in Neural Information Processing Systems

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