Publications

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2022

Journals

[214] Y Hu, D Schlom, S Datta, K Cho "Interlayer Engineering of Band Gap and Hole Mobility in p-Type Oxide SnO" ACS Applied Materials & Interfaces (May 2022)

[213] Y Luo, S Dutta, A Kaul, S Kyu Lim, M Bakir, S Datta, S Yu "A Compute-in-Memory Hardware Accelerator Design with Back-end-of-line (BEOL) Transistor based Reconfigurable Interconnect" IEEE Journal on Emerging and Selected Topics in Circuits and Systems (May 2022)

[212]  S Dutta, G Detorakis, A Khanna, B Grisafe, E Neftci, S  Datta "Neural sampling machine with stochastic synapse allows brain-like learning and inference" Nature Communications (May 2022)

[211] S Cheema, N Shanker, L Wang, C Hsu, S Hsu, Y Liao.... S Salahuddin "Ultrathin ferroic HfO2–ZrO2 superlattice gate stack for advanced transistors" Nature (April 2022)

[210] Y Lee, Y Hu, D Kim, S Datta, K Cho "First-principles mobility prediction for amorphous semiconductors" Physical Review B (Feb 2022)

[209] S Dutta, H Ye, AA Khandker, SG Kirtania, A Khanna, K Ni, S Datta "Logic Compatible High-Performance Ferroelectric Transistor Memory" IEEE Electron Device Letters (Feb 2022)

[208] KA Aabrar, SG Kirtania, FX Liang, J Gomez, M San Jose, Y Luo, H Ye, S Dutta, P Ravikumar, P Ravindran, A Khan, S Yu, S Datta "BEOL-Compatible Superlattice FEFET Analog Synapse With Improved Linearity and Symmetry of Weight Update" IEEE Transactions on Electron Devices (Jan 2022)

[207] DV Christensen, R Dittmann, B Linares-Barranco, A Sebastian, M Le Gallo, A Redaelli, S Slesazeck, T Mikolajick, S Spiga, S Menzel, I Valov, G Milano, C Ricciardi, S Liang, F Miao, M Lanza, T J Quill, S T Keene, A Salleo, ... N Pryds "2022 roadmap on neuromorphic computing and engineering" Neuromorphic Computing and Engineering (Jan 2022)

Conferences

 

2021

Journals

[206] Y Liao, K Akif Aabrar, W Chakraborty, W Li, S Datta, and S Salahuddin "Large Injection Velocities in Highly Scaled, Fully Depleted Silicon on Insulator Transistors" IEEE Electron Device Letters (Dec 2021)

[205] R Saligram, W Chakraborty, N Cao, Y Cao, S Datta, A Raychowdhury "Power Performance Analysis of Digital Standard Cells for 28nm Bulk CMOS at Cryogenic Temperature using BSIM models" IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (Nov 2021)

[204] W Chakraborty, K Akif Aabrar, J Gomez, R Saligram, A Raychowdhury, P Fay, and S Datta "Characterization and Modeling of 22nm FDSOI Cryogenic RF CMOS" IEEE Journal on Exploratory Solid-State Computational Devices and Circuits (Nov 2021)

[203] J A Smith, K Ni, H Takeuchi, RJ Stephenson, Y Chen, M Hytha, S Li, P E Nicollian, R J Mears, and S Datta "Intermixing reduction in ultra-thin titanium nitride/hafnium oxide film stacks grown on oxygen-inserted silicon and associated reduction of the interface charge dipole," Journal of Applied Physics 130, 185303 (2021); https://doi.org/10.1063/5.0068002 (Nov 2021)

[202] R Saligram, S Datta, A Raychowdhury "CryoMem: A 4–300-K 1.3-GHz Hybrid 2T-Gain-Cell-Based eDRAM Macro in 28-nm Logic Process for Cryogenic Applications" IEEE Solid-State Circuits Letters (Oct 2021)

201] R Saligram, S Datta, and A Raychowdhury "Scaled Back End of Line Interconnects at Cryogenic Temperatures" IEEE Electron Device Letters 42 (11), 1674-1677 (Oct 2021)

[200] S Dutta, A Khanna, AS Assoa, H Paik, DG Schlom, Z Toroczkai, A Raychowdhury, and S Datta "An Ising Hamiltonian solver based on coupled stochastic phase-transition nano-oscillators" Nature Electronics, (July 2021)

[199] M Si, A Murray, Z Lin, J Andler, J Li, J Noh, S Alajlouni, C Niu, X Lyu, D Zheng, K Maize, A Shakouri, S Datta, R Agrawal, and PD Ye "BEOL Compatible Indium-Tin-Oxide Transistors: Switching of Ultrahigh-Density 2-D Electron Gas Over 0.8 × 1014/cm2 at Oxide/Oxide Interface by the Change of Ferroelectric Polarization" IEEE Transactions on Electron Devices IEEE Transactions on Electron Devices (July 2021)

[198]  S Dutta, H Ye, A Khanna, Y Luo, L Pentecost, A A Khandker, W Chakraborty, G Wei, D Brooks, M Niemier, X Sharon Hu, S Yu, K Ni, and S Datta "Logic Compatible High-Performance Ferroelectric Transistor Memory" arXiv preprint arXiv:2105.11078 (May 2021)

[197]  D V Christensen ... N Pryds   "2021 roadmap on neuromorphic computing and engineering" arXiv preprint arXiv:2105.05956 (May 2021)

[196] S Cheema, N Shanker, L Wang, C Hsu, S Hsu, Y Liao, M San Jose, JGomez, W Li, J Bae, S Volkman, D Kwon, Y Rho, G Pinelli, Ra Rastogi, D Pipitone, C Stull, M Cook, B Tyrrell, V Stoica, Z Zhang, J Freeland, C Tassone, A Mehta, G Soheli, D Thompson, D Ik Suh, W Koo, K  Nam, D Jung, W Song, C  Lin, S Nam, J Heo, C Grigoropoulos, P Shafer, P Fay, R Ramesh, Jim Ciston, Suman Datta, Mohamed Mohamed, C Hu, S Salahuddin "Atomic-scale ferroic HfO2-ZrO2 superlattice gate stack for advanced transistors" Nature Portfolio DOI: 10.21203/rs.3.rs-413053/v1 (April 2021)

[195] X Ren, J Gomez, M K Bashar, J Ji, U Can, H Chang, N Shukla, S Datta, and P Zorlutuna "Cardiac Muscle Cell‐Based Coupled Oscillator Network for Collective Computing" Advanced Intelligent Systems published: 14 January 2021 https://doi.org/10.1002/aisy.202000253 (April 2021)

[194] N Tasneem, P Venkatesan Ravindran, Z Wang, J Gomez, J Hur, S Yu, S Datta, and A Khan "Differential charge boost in hysteretic ferroelectric–dielectric heterostructure capacitors at steady state" Applied Physics Lett. 118, 122901 (March 2021) 

[193] M Si, A Murray, Z Lin, J Andler, J Li, J Noh, S Alajlouni, C Niu, X Lyu, D Zheng, K Maize, A Shakouri, S Datta, R Agrawal, and P Ye "BEOL Compatible Indium-Tin-Oxide Transistors: Switching of Ultrahigh-Density 2-D Electron Gas Over 0.8 x 10¹⁴/cm² at Oxide/Oxide Interface by the Change of Ferroelectric Polarization" IEEE Transactions on Electron Devices  (March 2021) 

[192] B Chakrabarti, H Chan, K Alam, A Koneru, T E Gage, L E Ocola, R Divan, D Rosenmann, A Khanna, B Grisafe, T Sanders, S Datta, I Arslan, S KRS Sankaranarayan, and S Guha "Nanoporous Dielectric Resistive Memories Using Sequential Infiltration Synthesis" ACS nano March 2021

[191] S Dutta, G Detorakis, A Khanna, B Grisafe, E Neftci, and S Datta "Neural Sampling Machine with Stochastic Synapse allows Brain-like Learning and Inference" arXiv preprint arXiv:2102.10477 

[190] S Dutta, B Grisafe, C Frentzel, Z Enciso, M San Jose, J Smith, K Ni, S Joshi, and S Datta "Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security" IEEE Transactions on Electron Devices 68 (2), 516-522 Jan 2021

Conferences

[201] Y Hu, W Chakraborty, H Ye, S Datta, K Cho "First-principles investigation of amorphous n-type In2 O3 for BEOL transistor" 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

[200] W Chakraborty, KA Aabrar, J Gomez, R Saligram, A Raychowdhury, P Fay, S Datta "Cryogenic RF CMOS on 22nm FDSOI Platform with Record fT=495GHz and fMAX=497GHz" 2021 Symposium on VLSI Technology (June 2021)

[199] W Chakraborty, MS Jose, J Gomez, A Saha, KA Aabrar, P Fay, S Gupta, S Datta "Higher-k Zirconium Doped Hafnium Oxide (HZO) Trigate Transistors with Higher DC and RF Performance and Improved Reliability," 2021 Symposium on VLSI Technology (June 2021)

[198] P Wang, X Peng, W Chakraborty, A Khan, S Datta, and S Yu "Cryogenic Performance for Compute-in-Memory based Deep Neural Network Accelerator" 2021 IEEE International Symposium on Circuits and Systems (ISCAS)

[197] R Saligram, S Datta, and A Raychowdhury "CryoMem: A 4K-300K 1.3 GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications" 2021 IEEE Custom Integrated Circuits Conference (CICC)

[196] YC Luo, S Datta, and S Yu "Three-dimensional (3D) Non-volatile SRAM with IWO Transistor and HZO Ferroelectric Capacitor" 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)

[195]  P Wang, X Peng, W Chakraborty, A Khan, S Datta, and S Yu "Cryogenic Performance for Compute-in-Memory based Deep Neural Network Accelerator" 2021 IEEE International Symposium on Circuits and Systems (ISCAS)

2020

Journals

[189] Y Hu, X Yao, DG Schlom, S Datta, K Cho "First Principles Design of High Hole Mobility p-Type Sn–O–X Ternary Oxides: Valence Orbital Engineering of Sn2+ in Sn2+–O–X by Selection of Appropriate Elements X" Chemistry of Materials Dec 2020

[188] W Chakraborty, H Ye, B Grisafe, I Lightcap, and S Datta "Low Thermal Budget (<250 °C) Dual-Gate Amorphous Indium Tungsten Oxide (IWO) Thin-Film Transistor for Monolithic 3-D Integration" IEEE Transactions on Electron Devices Vol, 67. No 12, pp 5336-5342 Nov 2020

[187] K Berggren, Q Xia, K K Likharev, D B Strukov,….., J Yang, K Roy, S Datta, and A Raychowdhury "Roadmap on Emerging Hardware and Technology for Machine Learning" Nanotechnology Vol 32 Issue 1 pp 012002 Oct 2020

[186] A Khan, A Keshavarzi, and S Datta "The Future of Ferroelectric Feld-effect Transistor Technology" Nature Electronics  Oct 2020

[185] A Keshavarzi, K Ni, W Van Den Hoek, S Datta, and A Raychowdhury "FerroElectronics for Edge Intelligence"  IEEE Micro Sept 2020

[184] M Si, J Andler, X Lyu, C Niu, S Datta, R Agrawal, and P Ye "Indium-Tin-Oxide Transistors with One Nanometer Thick Channel and Ferroelectric Gating" ACS Nano Aug 2020

[183]  P Wang, Z Wang, X Sun, J Hur, S Datta, A Khan, and S Yu "Investigating Ferroelectric Minor Loop Dynamics and History Effect--Part II: Physical Modeling and Impact on Neural Network Training" IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2020.3009956 Volume: 67 , Issue: 9 , Sept. 2020

[182] S Dutta, A Khanna, H Paik, D Schlom, A Raychowdhury, Z Toroczkai, and S Datta "Ising Hamiltonian Solver using Stochastic Phase-Transition Nano-Oscillators" arXiv preprint arXiv:2007.12331 Jul 24, 2020

[181] C Wu, H Ye, B Grisafe, S Datta and P Fay  "Ferroelectric Polarization Switching Behavior of Hf0.5Zr0.5O2 Gate Dielectrics on Gallium Nitride High‐Electron‐Mobility‐Transistor Heterostructures" Physica Status Solidi (a) https://doi.org/10.1002/pssa.201900717 April 2020

[180] S Dutta, C Shafer, J Gomez, K Ni, S Joshi, S Datta "Supervised Learning in All FeFET-Based Spiking Neural Network: Opportunities and Challenges" Frontiers in Neuroscience Jun 2020 DOI:10.3389/fnins.2020.00634

[179] A Kazemi, R Rajaei, K Ni, S Datta, M Niemier, XS Hu "A Hybrid FeMFET-CMOS Analog Synapse Circuit for Neural Network Training and Inference" arXiv preprint arXiv:2004.00703

[178] B Bhar, A Khanna, A Parihar, S Datta, A Raychowdhury "Stochastic Resonance in insulator-Metal-transition Systems" Scientific Reports 10 (1), 1-11

[177] P Wang, W Shim, Z Wang, J Hur, S Datta, AI Khan, S Yu  "Drain-Erase Scheme in Ferroelectric Field Effect Transistor--Part II: 3-D-NAND Architecture for In-Memory Computing" IEEE Transactions on Electron Devices Volume: 67 , Issue: 3 , Mar. 2020

[176] P Wang, W Shim, Z Wang, J Hur, S Datta, AI Khan, S Yu "Drain-Erase Scheme in Ferroelectric Field-Effect Transistor--Part I: Device Characterization" IEEE Transactions on Electron Devices Volume: 67 , Issue: 3 , March 2020

[175] Y Liang, Z Zhu, X Li, SK Gupta, S Datta, V Narayanan "Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance" IEEE Transactions on Electron Devices  Volume: 67 , Issue: 3 , Mar. 2020

[174] E Corti, A Khanna, K Niang, J Robertson, K Moselund, B Gotsamnn,S Datta, S Karg "Time-delay encoded image recognition in a network of resistively-coupled VO2 on Si oscillators" IEEE Device Letters  Feb 2020 DOI: 10.1109/LED.2020.2972006

[173] C Wu, H Ye, N Shaju, J Smith, B Grisafe, S Datta, and P Fay "Hf0. 5Zr0. 5O2 Based Ferroelectric Gate HEMTs (FeHEMTs) with Large Threshold Voltage Tuning Range" IEEE Electron Device Letters Jan 9, 2020 DOI: 10.1109/LED.2020.2965330.

[172] J Park, H Paik, K Nomoto, Ki Lee, B Park, B Grisafe, L Wang, S Salahuddin, S Datta, Y Kim, D Jena, HG Xing, and D Schlom "Fully transparent field-effect transistor with high drain current and on-off ratio" APL Materials Vol 8 Issue 1>10.1063/1.5133745 

Conferences

[194]  S Deng, Z Jiang, S Dutta, H Ye, W Chakraborty, S Kurinec, S Datta, and K Ni "Examination of the Interplay Between Polarization Switching and Charge Trapping in Ferroelectric FET" 2020 IEEE International Electron Devices Meeting (IEDM), 4.4. 1-4.4. 4

[193]  P Wang, X Peng, W Chakraborty, AI Khan, S Datta, and S Yu "Cryogenic Benchmarks of Embedded Memory Technologies for Recurrent Neural Network based Quantum Error Correction" 2020 IEEE International Electron Devices Meeting (IEDM), 38.5. 1-38.5. 4

[192]  X Peng, W Chakraborty, A Kaul, W Shim, MS Bakir, S Datta, and S Yu "Benchmarking Monolithic 3D Integration for Compute-in-Memory Accelerators: Overcoming ADC Bottlenecks and Maintaining Scalability to 7nm or Beyond" 2020 IEEE International Electron Devices Meeting (IEDM), 30.4. 1-30.4. 4

[191]  S Dutta, H Ye, W Chakraborty, YC Luo, M San Jose, B Grisafe, A Khanna, I Lightcap, S Shinde, S Yu, and S Datta "Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory" 2020 IEEE International Electron Devices Meeting (IEDM), 36.4. 1-36.4. 4

[190]  H Ye, J Gomez, W Chakraborty, S Spetalnick, S Dutta, K Ni, A Raychowdhury, and S Datta "Double-Gate W-Doped Amorphous Indium Oxide Transistors for Monolithic 3D Capacitorless Gain Cell eDRAM" 2020 IEEE International Electron Devices Meeting (IEDM), 28.3. 1-28.3. 4

[189]  A Kumar Sahu, M Si, K Ni, S Datta, P Ye, andS K Gupta "Ferroelectric thickness dependent domain interactions in FEFETs for memory and logic: A phase-field model based analysis" 2020 IEEE International Electron Devices Meeting (IEDM), 4.3. 1-4.3. 4

[188] S Deng, G Yin, W Chakraborty, S Dutta, S Datta, X Li, and K Ni "A Comprehensive Model for Ferroelectric FET Capturing the Key Behaviors: Scalability, Variation, Stochasticity, and Accumulation" 2020 IEEE Symposium on VLSI Technology, 1-2

[187] A Khanna, E Elmitwalli, S Dutta, S Deng, S Datta, S Köse, and K Ni "A Bias and Correlation Free True Random Number Generator Based on Quantized Oscillator Phase under Sub-Harmonic Injection Locking" 2020 IEEE Symposium on VLSI Technology, 1-2 

[186] W Chakraborty, B Grisafe, H Ye, I Lightcap, K Ni, and S Datta "BEOL Compatible Dual-Gate Ultra Thin-Body W-Doped Indium-Oxide Transistor with . SS = 73mV/dec and  ratio > 4×109" 2020 IEEE Symposium on VLSI Technology, 1-2

[185] W Chakraborty, U Sharma, S Datta, and S Mahapatra  "Hot Carrier Degradation in Cryo-CMOS" 2020 IEEE International Reliability Physics Symposium (IRPS) April 2020

[184] K Ni, S Dutta, S Datta, “Ferroelectrics: From Memory to Computing” 25th IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) 401-406. Jan 2020

2019

Journals

[171] K Ni, X. Yin, AF Laguna, S Joshi, S Dunkel, M Trentzsch, J Muller, S Beyer, M Niemier, X S Hu, and S Datta "Ferroelectric ternary content-addressable memory for one-shot learning" Nature Electronics  Nov 2019 2 (11), 521-529

[170]  X Chen, S Datta, XS Hu, M Jerry, AF Laguna, K Ni, M Niemier, D Reis, X Sun, P Wang, X Yin, and S Yu " The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures" IEEE Design & Test Oct 2019 DOI: 10.1109/MDAT.2019.2944094

[169] I Yoon, M Jerry, S Datta, and A Raychowdhury "Design Space Exploration of Ferroelectric FET based Processing -in-Memory"  Aug 2019 arXiv preprint arXiv:1908.07942

[168] V Misra, A Bozkurt, BH Calhoun, S Datta, M Dickey, M Kiani, J Lach, B Lee, J Jur, O Oralkan, M Ozturk, R. Rajagopalan, S Roundy, J Strohmaier, S Trolier-McKinstry, D Vashaee, D Wentzloff and D Werner "Optimizing the energy balance to achieve autonomous self-powering for vigilant health and IoT applications" Journal of Physics: Conference Series 1407 (1), 012001

[167] Y Hu, J Hwang, Y Lee, P Conlin, DG Schlom, S Datta, and K Cho, "First principles calculations of intrinsic mobilities in tin-based oxide semiconductors SnO, SnO2, and Ta2SnO6" Journal of Applied Physics 126 (18), 185701

[166] C Wu, H Ye, B Grisafe, S Datta, and P Fay, "Ferroelectric Polarization Switching Behavior of Hf0. 5Zr0. 5O2 Gate Dielectrics on Gallium Nitride High-Electron-Mobility-Transistor Heterostructures" Physica Status Solidi A-Applications and Materials Science 09 Nov. 2019 https://doi.org/10.1002/pssa.201900717

[165] S Datta, S Dutta, B Grisafe, J Smith, S Srinivasa, and H Ye, "Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration", IEEE Micro, vol 39 , Issue: 6 , 2019

[164] Y Liang, Z Zhu, X Li, SK Gupta, S Datta, and V Narayanan, “Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol , no , pp 2019

[163] B Grisafe, M Jerry, J A Smith, and S Datta, “Performance Enhancement of Ag/HfO2 Metal Ion Threshold Switch Cross-point Selectors”, IEEE Electron Device Letters, vol 40, no 10, pp 1602-1605, 2019

[162] S Dutta, A Parihar, A Khanna, J Gomez, W Chakraborty, M Jerry, B Grisafe, A Raychowdhury, and S Datta, “Programmable coupled oscillators for synchronized locomotion” Nature communications, vol 10, no 1, pp 3299, 2019

[161] D Reis, K Ni, W Chakraborty, X Yin, M Trentzsch, S Dünkel, T Melde, J Müller, S Beyer, S Datta, M Niemier, and X S Hu, “Design and analysis of an ultra-dense, low-leakage and fast FeFET-based random access memory array”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, July 2019

[160] I Yoon, M Chang, K Ni, M Jerry, S Gangopadhyay, G H Smith, T Hamam, J Romberg, V Narayanan, A Khan, S Datta, and A Raychowdhury, “A FerroFET based in-memory processor for solving distributed and iterative optimizations via least-squares method”, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, July 2019

[159] AK Saha, K Ni, S Dutta, S Datta, and S Gupta, “Phase field modeling of domain dynamics and polarization accumulation in ferroelectric HZO”, vol 114, no 20, pp 202903 Applied Physics Letters, 2019

[158] Y Fang, J Gomez, Z Wang, S Datta, AI Khan, and A Raychowdhury, “Neuro-mimetic Dynamics of a Ferroelectric FET Based Spiking Neuron” IEEE Electron Device Letters, vol 40, no 7, pp 1213-1216, 2019

[157] X Li, J Wu, K Ni, S George, K Ma, J Sampson, S K Gupta, Y Liu, H Yang, S Datta, and V Narayanan, “Design of 2T/cell and 3T/cell nonvolatile memories with emerging ferroelectric FETs”, IEEE Design and Test, vol 36, no 3, pp 39-45, 2019

[156] Z Shen, S Srinivasa, A Aziz, S Datta, V Narayanan, and S K Gupta, “SRAMs and DRAMs With Separate Read–Write Ports Augmented by Phase Transition Materials”, IEEE Transactions on Electron Devices, vol 66, no 2, pp 929-937, 2019

[155] Y Fang, Z Wang, J Gomez, S Datta, AI Khan, and A Raychowdhury, “A Swarm Optimization Solver Based on Ferroelectric Spiking Neural Networks” Frontiers Neuroscience 13, pp 855, 2019

[154] R Zhao, B Grisafe, R Ghosh, K Wang, S Datta, and J Robinson, “Stabilizing the commensurate charge-density wave in 1T-tantalum disulfide at higher temperatures via potassium intercalation” Nanoscale, vol 11, no 13, pp 6016-6022, 2019

[153] Z Shen, S Srinivasa, A Aziz, S Datta, V Narayanan, and S K Gupta, “SRAMs and DRAMs With Separate Read-Write Ports Augmented by Phase Transition Materials”, IEEE Transactions on Electron Devices, vol 66, no 2, pp. 929-937, 2019

[152] A Raychowdhury, A Parihar, G H Smith, V Narayanan, G Csaba, M Jerry, W Porod, and S Datta, “Computing With Networks of Oscillatory Dynamical Systems”, Proceedings of the IEEE, vol 107, no 1, pp. 73-89, 2019

Conferences

[183] S Dutta, A Khanna, J Gomez, K Ni, Z Toroczkai and S Datta, "Experimental Demonstration of Phase Transition Nano-Oscillator Based Ising Machine”, IEEE International Electron Devices Meeting (IEDM) 2019

[182] J. Gomez S. Dutta, K. Ni, J.A. Smith, B. Grisafe, A. Khan and S. Datta, "Hysteresis-free negative capacitance in the multi- domain scenario for logic applications”, IEEE International Electron Devices Meeting (IEDM) 2019

[181] K Ni, J Smith, H Ye, B Grisafe, G. B. Rayner, A Kummel, and S Datta, "A Novel Ferroelectric Superlattice Based Multi-Level Cell Non-Volatile Memory”, IEEE International Electron Devices Meeting (IEDM) 2019

[180] W Chakraborty, K Ni, J Smith, A Raychowdhury and S Datta, "An Empirically Validated Virtual Source FET Model for Deeply Scaled Cool CMOS”, IEEE International Electron Devices Meeting (IEDM) 2019

[179] K Ni, A Saha, W Chakraborty, H Ye, B Grisafe, J Smith, G B Rayner, S Gupta, S Datta, "Equivalent Oxide Thickness (EOT) Scaling With Hafnium Zirconium Oxide High-κ Dielectric Near Morphotropic Phase Boundary”, IEEE International Electron Devices Meeting (IEDM) 2019

[178] AK Saha, B Grisafe, S Datta, SK Gupta, “Microscopic Crystal Phase Inspired Modeling of Zr Concentration Effects in Hf1-xZrxO2Thin Films”, Symposium on VLSI Technology, T226-T227, June 2019

[177] S Dutta, A Saha, P Panda, W Chakraborty, J Gomez, A Khanna, S Gupta, S Datta, “Biologically Plausible Ferroelectric Quasi-Leaky Integrate and Fire Neuron”, Symposium on VLSI Technology, T140-T141, June 2019

[176] S Dutta, A Khanna, W Chakraborty, J Gomez, S Joshi, S Datta, “Spoken vowel classification using synchronization of phase transition nano-oscillators”, Symposium on VLSI Technology , T128-T129, June 2019

[175] K Ni, W Chakraborty, J Smith, B Grisafe, S Datta, “Fundamental Understanding and Control of Device-to-Device Variation in Deeply Scaled Ferroelectric FETs”, Symposium on VLSI Technology, T40-T41, June 2019

[174] S Dutta, W Chakraborty, J Gomez, K Ni, S Joshi, S Datta, “Energy-Efficient Edge Inference on Multi-Channel Streaming Data in 28nm HKMG FeFET Technology”, Symposium on VLSI Technology , T38-T39, June 2019

[173] P Cadareanu, CG Almudever, A Khanna, A Raychowdhury, S Datta, “Rebooting Our Computing Models”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 469-1476, Mar 2019

[172] J Gomez, S Dutta, K Ni, S Joshi, S Datta, “Steep Slope Ferroelectric Field Effect Transistor," Electron Devices Technology and Manufacturing Conference (EDTM), 59-61, Mar 2019

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2018

Journals

[151] X Chen, K Ni, MT Niemier, Y Han, S Datta, XS Hu, “Power and area efficient FPGA building blocks based on ferroelectric FETs”, IEEE Transactions on Circuits and Systems I: Regular Papers 66 (5), 1780-1793, 2018

[150] Xunzhao Yin, Kai Ni, Dayane Reis, Suman Datta, Michael Niemier, Xiaobo Sharon Hu, “An Ultra-dense 2FeFET TCAM Design based on a Multi-Domain FeFET Model”, IEEE Transactions on Circuits and Systems, 2018

[149] Yuhua Liang, Xueqing Li, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan, “Analysis of DIBL Effect and Negative Resistance Performance for NCFET Based on a Compact SPICE Model”, IEEE Transactions on Electron Devices, vol 65, no 12, pp. 5525-5529, 2018

[148] Kai Ni, Xueqing Li, Jeffrey A Smith, Matthew Jerry, Suman Datta, “Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays”, IEEE Electron Device Letters, vol 39, no 11, pp 1656-1659, 2018

[147] J-S Liu, M Clavel, R Pandey, S Datta, Y Xie, JJ Heremans, MK Hudait, “Heterogeneous integration of InAs/GaSb tunnel diode structure on silicon using 200 nm GaAsSb dislocation filtering buffer”, AIP Advances, vol 8, no 10, pp 105108, 2018

[146] Benjamin Grisafe, Rui Zhao, Ram Krishna Ghosh, Joshua A Robinson, Suman Datta, “Electrically triggered insulator-to-metal phase transition in two-dimensional (2D) heterostructures”, Applied Physics Letters, vol 113, no 14, pp. 142101, 2018

[145] S Datta, “Ten nanometer CMOS logic technology”, Nature Electronics, vol 1, no 9, pp-500-501, 2018

[145] Yuhua Liang, Xueqing Li, Sumitha George, Srivatsa Srinivasa, Zhangming Zhu, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan, “Influence of Body Effect on Sample-and-Hold Circuit Design Using Negative Capacitance FET”, IEEE Transactions on Electron Devices, vol 65, no 9, pp. 3909-3914, 2018

[144] Matthew Jerry, Sourav Dutta, Arman Kazemi, Kai Ni, Jianchi Zhang, Pai-Yu Chen, Pankaj Sharma, Shimeng Yu, X Sharon Hu, Michael Niemier, Suman Datta, “A Ferroelectric field effect transistor based synaptic weight cell”, Journal of Physics D; Applied Physics, vol 51, no 43, pp 434001-, 2018

[143] Sayeef Salahuddin, Kai Ni, Suman Datta, “The Era of Hyper-Scaling in Electronics”, Nature Electronics, vol 1, no 8, pp 442, 2018

[142] Xueqing Li, Sumitha George, Yuhua Liang, Kaisheng Ma, Kai Ni, Ahmedullah Aziz, Sumeet Kumar Gupta, John Sampson, Meng-Fan Chang, Yongpan Liu, Huazhong Yang, Suman Datta, Vijaykrishnan Narayanan, “Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops”, IEEE Transactions on Electron Devices, vol 65, no 6, pp. 2670-2674, 2018

[141] Kai Ni, Pankaj Sharma, Jianchi Zhang, Matthew Jerry, Jeffery A Smith, Kandabara Tapily, Robert Clark, Souvik Mahapatra, Suman Datta, “Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance”, IEEE Transactions on Electron Devices, vol 65, no 6, pp.2461-2469, 2018

[140] Abhinav Parihar, Matthew Jerry, Suman Datta, Arijit Raychowdhury, “Stochastic IMT (insulator-metal-transition) neurons: An interplay of thermal and threshold noise at bifurcation”, Frontiers in Neuroscience, vol 12, pp. 210, 2018

[139] Atanu K Saha, Suman Datta, Sumeet K Gupta, “Negative capacitance” in resistor-ferroelectric and ferroelectric-dielectric networks: Apparent or intrinsic?” Journal of Applied Physics, vol 123, no 10, pp 105102-, 2018

[138] Sushant Sonde, Bhaswar Chakrabarti, Yuzi Liu, Kiran Sasikumar, Jianqiang Lin, Liliana Stan, Ralu Divan, Leonidas E Ocola, Daniel Rosenmann, Pabitra Choudhury, Kai Ni, Subramanian KRS Sankaranarayanan, Suman Datta, Supratik Guha, “Silicon compatible Sn-based resistive switching memory”, Nanoscale, vol 10, non 20, pp 9441-9449, 2018

[137] R Zhao, B Grisafe, RK Ghosh, S Holoviak, B Wang, K Wang, N Briggs, A. Haque, S. Datta and J. Robinson, “Two-dimensional tantalum disulfide: controlling structure and properties via synthesis”, 2D Materials 5 (2), 025001, 2018

[136] M. Jerry, K. Ni, A. Parihar, A. Raychowdhury and S. Datta, “Stochastic Insulator-to-Metal Phase Transition based True Random Number Generator”, IEEE Electron Device Letters, vol 39, pp 139-142, no 1, Jan 2018

Conferences

[171] K Ni, JA Smith, B Grisafe, T Rakshit, B Obradovic, JA Kittl, M Rodder, S Datta, “SoC Logic Compatible Multi-Bit FeMFET Weight Cell for Neuromorphic Applications”, IEEE International Electron Devices Meeting (IEDM), 13.2. 1-13.2. 4, Dec 2018

[170] X Sun, P Wang, K Ni, S Datta, S Yu, “Exploiting Hybrid Precision for Training and Inference: A 2T-1FeFET Based Analog Synaptic Weight Cell”, IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, Dec 2018

[169] Z Wang, B Crafton, J Gomez, R Xu, A Luo, Z Krivokapic, L Martin, S Datta, A Khan, “Experimental Demonstration of Ferroelectric Spiking Neurons for Unsupervised Clustering”, IEEE International Electron Devices Meeting (IEDM), 13.3. 1-13.3. 4, Dec 2018

[168] K Ni, B Grisafe, W Chakraborty, AK Saha, S Dutta, M Jerry, JA Smith, S Datta, “In-Memory Computing Primitive for Sensor Data Fusion in 28 nm HKMG FeFET Technology”, IEEE International Electron Devices Meeting (IEDM), 16.1. 1-16.1. 4, Dec 2018

[167] Robert D Clark, Kandabara Tapily, Steven Consiglio, Cory S Wajda, Kai Ni, Sonal Dey, Vineetha Mukundan, K Beckman, Gert J Leusink, Nathaniel Cady, Alain C Diebold, S Datta, “Teaching a New Dog Old Tricks: Ferroelectric HfZrO Films and Devices”, The Electrochemical Society Meeting Abstracts, pp 696, July 2018

[166] Abhinav Parihar, Anvesha Amravati, Matthew Jerry, Suman Datta, Arijit Raychowdhury, “Dynamics of Coupled Systems and their Computing Properties”, 2018 16th IEEE International New Circuits and Systems Conference (NEWCAS), pp 361-364, Jun 2018

[165] ]M Jerry, JA Smith, K Ni, A Saha, S Gupta, S Datta, “Insights on the DC Characterization of Ferroelectric Field-Effect-Transistors”, 2018 76th Device Research Conference (DRC), 1-2, Ju 2018

[164] A Aziz, N Shukla, A Seabaugh, S Datta, S Gupta, “Cockcroft-Walton Multiplier based on UnipolarThreshold Switch”, 2018 76th Device Research Conference (DRC), 1-2, June 2018

[163] JA Smith, H Takeuchi, R Stephenson, YA Chen, M Hytha, RJ Mears, S Datta, “Experimental Investigation of N-Channel Oxygen-Inserted (OI) Silicon Channel MOSFETs with High-K/Metal Gate Stack”, 2018 76th Device Research Conference (DRC), 1-2, Jun 2018

[162] B Grisafe, S Datta, “Investigation of Threshold Switch OFF-State Resistance on Performance Enhancement in 2D Mos2 Phase-FETs”, 2018 76th Device Research Conference (DRC), Jun 2018

[161] I Yoon, M Chang, K Ni, M Jerry, S Gangopadhyay, G Smith, T Hamam, S Datta, “A FeFET Based Processing-In-Memory Architecture for Solving Distributed Least-Square Optimizations”, 76th Device Research Conference (DRC), 1-2, Jun 2018
[156] Kai Ni, Matthew Jerry, Jeffrey A Smith, Suman Datta, “A circuit compatible accurate compact model for ferroelectric-FETs”, 2018 IEEE Symposium on VLSI Technology, pp 131-132, Jun 2018

[160] M Jerry, A Aziz, K Ni, S Datta, Sumeet Kumar Gupta, N Shukla, “A Threshold Switch Augmented Hybrid-FeFET (H-FeFET) with Enhanced Read Distinguishability and Reduced Programming Voltage for Non-Volatile Memory Applications”, 2018 IEEE Symposium on VLSI Technology, pp129-130, Jun 2018

[159] Gyorgy Csaba, Arijit Raychowdhury, Suman Datta, Wolfgang Porod, “Computing with Coupled Oscillators: Theory, Devices, and Applications”, Circuits and Systems (ISCAS), 2018 IEEE International Symposium on, pp 1-5, May 2018

[158] Benjamin Grisafe, Rui Zhao, Matthew Jerry, Joshua A Robinson, Suman Datta, “Investigation of the abrupt phase transition in 1T-TaS2/MoS2heterostructures”, 2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp 1-2, Apr 2018

[157] Ahmedullah Aziz, Evelyn T Breyer, An Chen, Xiaoming Chen, Suman Datta, Sumeet Kumar Gupta, Michael Hoffmann, Xiaobo Sharon Hu, Adrian Ionescu, Matthew Jerry, Thomas Mikolajick, Halid Mulaosmanovic, Kai Ni, Michael Niemier, Ian O'Connor, Atanu Saha, Stefan Slesazeck, Sandeep Krishna Thirumala, Xunzhao Yin, “Computing with ferroelectric FETs: Devices, models, systems, and applications”, Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1289-1298, Mar 2018

[156] S Datta, A Kummel, “Technology Innovations in Selective ALD for Next-Generation Contacts and Vias”, 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), pp 102-103, Mar 2018

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2017

Journals

[135] P. Sharma, J. Zhang, K. Ni and S. Datta, "Time-Resolved Measurement of Negative Capacitance," in IEEE Electron Device Letters, vol. PP, no. 99, pp. 1-1, 2017

[134] Hideki Takeuchi, Robert J Mears, Robert J Stephenson, Marek Hytha, Daniel Connelly, Pavel Fastenko, Richard Burton, Nyles W Cody, Doran Weeks, Dmitri Choutov, Nidhi Agrawal, Suman Datta, "Punch-Through Stop Doping Profile Control via Interstitial Trapping by Oxygen-Insertion Silicon Channel," in IEEE Journal of the Electron Devices Society, vol. PP, no. 99, pp. 1-1, 2017

[133] P. J. Drummond, A. Wali, M. J. Barth, A. M. Diehm, S. Datta, J. Ruzyllo, “Photoconductance Decay Characterization of 3D Multi-Fin Silicon on SOI Substrates”, IEEE Transactions on Electron Devices, vol., no. 99, pp., 2017.

[132] Li, S. George, K. Ma, W.-Y Tsai, A. Aziz, J. Sampson, S. K. Gupta, M.-F. Chang, Y. Liu, S. Datta, and V. Narayanan, “Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol., no. 99 pp. 1-13, 2017.

[131] C. Schulte-Braucks, R. Pandey, R. N. Sajjad, M. Barth, R. K. Ghosh, B. Grisafe, P. Sharma, N. von den Driesch, A. Vohra, G. B. Rayner, R. Loo, S. Mantl, D. Buca, C.-C. Yeh, C.-H. Wu, W. Tsai, D. A. Antoniadis, S. Datta, “Fabrication, Characterization, and Analysis of Ge/GeSn Heterojunction p-Type Tunnel Transistors”, IEEE Transactions on Electron Devices, vol. 64, no. 10, pp. 4354-4362, 2017.

[130] D. Li, A. A Sharma, N. Shukla, H. Paik, J. M. Goodwill, S. Datta, D. G. Schlom, J. A. Bain, M. Skowronski, “ON-state evolution in lateral and vertical VO2 threshold switching devices”, IOP Nanotechnology, vol. 28, no. 40, pp. 405201, 2017.

[129] S. Gupta, M. Steiner, A. Aziz, V. Narayanan, S. Datta, S. K. Gupta, “Device-Circuit Analysis of Ferroelectric FETs for Low-Power Logic”, IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3092-3100, 2017.

[128] X. Li, J. Sampson, A. Khan, K. Ma, S. George, A. Aziz, S. K. Gupta, S. Salahuddin, M.-F. Chang, S. Datta, V. Narayanan, “Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET”, IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3452-3458, 2017.

[127] X. Li, K. Ma, S. George, W.-S. Khwa, J. Sampson, S. Gupta, Y. Liu, M.-F. Chang, S. Datta, and V. Narayanan, “Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore”, IEEE Transactions on Electron Devices, vol. 64, no. 7, pp. 3037 – 3040, July 2017.

[126] X. Li, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Meng-Fan Chang, Yongpan Liu, Suman Datta, Vijaykrishnan Narayanan, “Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol xx, pp yy, pp 1-13, 2017

[125] Yuanxia Zheng, Sungwook Hong, George Psofogiannakis, G Bruce Rayner Jr, Suman Datta, Adri CT van Duin, Roman Engel-Herbert, “Modeling and in Situ Probing of Surface Reactions in Atomic Layer Deposition”, ACS Applied Materials & Interfaces, vol 9, no 18, pp 15848-15856, 2017

[124] Quentin Smets, Anne Verhulst, Ji-Hong Kim, Jason P Campbell, David Nminibapiel, Dmitry Veksler, Pragya Shrestha, Rahul Pandey, Eddy Simoen, David Gundlach, Curt Richter, Kin P Cheung, Suman Datta, Anda Mocuta, Nadine Collaert, Aaron V-Y Thean, Marc M Heyns, “Pulsed IV on TFETs: Modeling and Measurements”, IEEE Transactions on Electron Devices, vol 64, no 4, pp 1489-1497, 2017

[123] Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta, Arijit Raychowdhury, “Computing with dynamical systems based on insulator-metal-transition oscillators”, Nature Scientific Reports, vol 6, no 3, pp 601-611, 2017

[122] A. Aziz, N. Shukla, S. Datta, and S. K. Gupta, "Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective—Part II", IEEE Trans. Elec. Dev., Vol. 64, No. 3, pp. 1358-1365, March 2017.

[121] M. Brahlek, L. Zhang, J. Lapano, H.-T. Zhang, R. Engel-Herbert, N. Shukla, S. Datta, H. Paik, D. G. Schlom, "Opportunities in vanadium-based strongly correlated electron systems", MRS Communications, pp. 1-26, Feb. 2017. doi: 10.1557/mrc.2017.2.

[120] Y. J. Li, C. Y. Huang, C. C. Wu, Y. C. Chen, C. Y. Wang, S. Datta, V. Narayanan, "Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. , no.99, pp. 1-13, 2017.

[119] S. Advani, P. Zientara, N. Shukla, I. Okafor, K. Irick, J. Sampson, S. Datta, V. Narayanan, "A Multitask Grocery Assist System for the Visually Impaired: Smart glasses, gloves, and shopping carts provide auditory and tactile feedback", IEEE Consumer Electronics Magazine, vol. 6, no. 1, pp. 73-81, 2017.

Conferences

[155] Nikhil Shukla, Ram Krishna Ghosh, and Benjamin Grisafe, "Fundamental Mechanism behind Volatile and Non-volatile Switching in Metallic Conducting Bridge RAM," 2017 IEDM Conference, San Francisco, CA.

[154] Jeffrey A Smith, Kai Ni, Ram Krishna Ghosh, Jeff Xu, Mustafa Badaroglu, PR Chidi Chidambaram, Suman Datta, "Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications," 2017 47th European Solid-State Device Research Conference (ESSDERC), Leuven, 2017, pp. 188-191.

[153] Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung-Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta, David Kohen, Po-Wen Chan, Keagan Chen, PR Chidi Chidambaram, "PPAC scaling enablement for 5nm mobile SoC technology," 2017 47th European Solid-State Device Research Conference (ESSDERC), Leuven, 2017, pp. 240-243.

[152] A. Aziz, N. Jao, S. Datta, V. Narayanan and S. K. Gupta, "A computationally efficient compact model for leakage in cross-point array," 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, 2017, pp. 141-144.

[151] S Datta, A Seabaugh, M Niemier, A Raychowdhury, D Schlom, D Jena, “In quest of the next information processing substrate”, Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE, 1-6

[150] P Sharma, J Zhang, AK Saha, S Gupta, S Datta, “Negative capacitance transients in metal-ferroelectric Hf 0.5 Zr 0.5 O 2-Insulator-Semiconductor (MFIS) capacitors,” Device Research Conference (DRC), 2017 75th Annual, 1-2

[149] A. Aziz, X. Li, N. Shukla, S. Datta, M.-F. Chang, V. Narayanan, S. K. Gupta, “Low power current sense amplifier based on phase transition material”, 75th Annual Device Research Conference (DRC), pp. 1-2, 2017

[148] K. Ni, J. A. Smith, M. Barth, H. Liu, J. H. Warner, K. Saraswat, S. Datta, “Soft error evaluation for InGaAs and Ge complementary FinFETs”, 75th Annual Device Research Conference (DRC), pp. 1-2, 2017.

[147] J. A. Smith, M. Barth, K. Ni, M. Cantoro, D.-W. Kim, S. Datta, “Corrugated channel In 0.8 Ga 0.2 As quantum well transistors for low power logic applications”, 75th Annual Device Research Conference (DRC), pp. 1-2, 2017.

[146] M. Jerry, A. Parihar, A. Raychowdhury, S. Datta, “A random number generator based on insulator-to-metal electronic phase transitions”, 75th Annual Device Research Conference (DRC), pp. 1-2, 2017.

[145] S. Datta, A. Seabaugh, M. Niemier, A. Raychowdhury, D. Schlom, D. Jena, G. Xing, H-S Philip Wong, E. Pop, S. Salahuddin, S. Gupta, S. Guha, “In Quest of the Next Information Processing Substrate: Extended Abstract”, Proceedings of the 54th Annual Design Automation Conference, pp. 17, 2017.

[144] P. Sharma, K. Tapily, A. K. Saha, J. Zhang, A. Shaughnessy, A. Aziz, G. L. Snider, S. Gupta, R. D. Clark, S. Datta, “Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack”, IEEE Symposium on VLSI Circuits, pp. T154-T155, 2017.

[143] M Jerry, A Parihar, B Grisafe, A Raychowdhury, S Datta, “Ultra-low power probabilistic IMT neurons for stochastic sampling machines” IEEE Symposium on VLSI Technology, Kyoto, June 2017

[142] Abhinav Parihar, Nikhil Shukla, Matthew Jerry, Suman Datta, Arijit Raychowdhury, “Computational paradigms using oscillatory networks based on state-transition devices”, International Joint Conference on Neural Networks (IJCNN), 14-19 May, 2017

[141] Benjamin Grisafe, Nikhil Shukla, Matthew Jerry, Suman Datta, “A steep slope Phase-FET based on 2D MoS 2 and the electronic phase transition in VO 2” VLSI Technology, Systems and Application (VLSI-TSA), 2017 International Symposium on, pp 1-2, 2017

[140] Sumeet Kumar Gupta, Danni Wang, Sumitha George, Ahmedullah Aziz, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan, “Harnessing ferroelectrics for non-volatile memories and logic”, Quality Electronic Design (ISQED), 2017 18th International Symposium on, pp 29-34, 2017

[139] Robert J Mears, Hideki Takeuchi, Robert J Stephenson, Marek Hytha, Richard Burton, Nyles W Cody, Doran Weeks, Dmitri Choutov, Nidhi Agrawal, Suman Datta, “Punch-through stop doping profile control via interstitial trapping by oxygen-insertion silicon channel”, Electron Devices Technology and Manufacturing Conference (EDTM), 2017 IEEE, pp 65-66, 2017

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2016

Journals

[118] J.-S. Liu, M. B. Clavel, R. Pandey, S. Datta, M. Meeker, G. A. Khodaparast, and M. K Hudait, "Growth and characterization of metamorphic InAs/GaSb tunnel heterojunction on GaAs by molecular beam epitaxy", J. Appl. Phys., vol. 119, no. 24, pp. 244308, 2016.

[117] M. Barth, A. Kumar, J. H. Warner, B. R. Bennett, B. Boos, C. D. Cress, N. J-H Roche, M. Raine, M. Gaillardin, P. Paillet, D. McMorrow, K. Saraswat, S. Datta, "Single-Event Measurement and Analysis of Antimony-Based p-Channel Quantum-Well MOSFETs with High-κ Dielectric", IEEE Trans. Nuc. Sci., no. 99, 2016.

[116] A. Aziz, N. Jao, S. Datta, S. K. Gupta, "Analysis of Functional Oxide based Selectors for Cross-Point Memories", IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 63, no. 12, pp. 2222-2235, 2016.

[115] R. Pandey, S. Mookerjea, S. Datta, "Opportunities and Challenges of Tunnel FETs", IEEE Trans. Circuits and Systems I: Regular Paper, vol. 63 no. 12, pp. 2128-2138, 2016.

[114] S. Srinivasa, A. Aziz, N. Shukla, X. Li, J. Sampson, S. Datta, J. P. Kulkarni, V. Narayanan, S. K. Gupta, "Correlated Material Enhanced SRAMs With Robust Low Power Operation", IEEE Trans. Elec. Dev. vol. 63, no. 12, pp. 4744-4752, 2016.

[113] C.H. Ho, Y.C. Chen, C.Y. Wang, C.Y. Huang, S. Datta, V. Narayanan, "Area-Aware Decomposition for Single-Electron Transistor Arrays", ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 21, no. 4, pp. 70, 2016.

[112] H.‐T. Zhang, L. Guo, G. Stone, L. Zhang, Y.‐X. Zheng, E. Freeman, D. W. Keefer, S. Chaudhuri, H. Paik, J. A. Moyer, M. Barth, D. G. Schlom, J. V. Badding, S. Datta, V. Gopalan, R. Engel‐Herbert, "Imprinting of Local Metallic States into VO2 with Ultraviolet Light", J. Adv. Func. Mat., vol. 26, no. 36, pp. 6612-6618, 2016.

[111] Z. Y. A. Balushi, K. Wang, R. K. Ghosh, R. A. Vilá, S. M. Eichfeld, J. D. Caldwell, X. Qin, Y.-C. Lin, P. A. DeSario, G. Stone, S. Subramanian, D. F. Paul, R. M. Wallace, S. Datta, J. M. Redwing, J. A. Robinson, "Two-dimensional gallium nitride realized via graphene encapsulation", Nature Materials, vol. 15, pp. 1166–1171, 2016.

[110] M.S. Kim, W. C.-Wissing, X. Li, J. Sampson, S. Datta, S.K. Gupta, V. Narayanan, "Comparative area and parasitics analysis in FinFET and heterojunction vertical TFET standard cells", ACM J. on Emerging Tech. in Computing Systems (JETC), vol. 12, no. 4, pp. 38, 2016.

[109] C.Y. Huang, Y.J. Li, C.W. Liu, C.Y. Wang, Y.C. Chen, S. Datta, V. Narayanan,"Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 6, pp. 2321-2334, 2016.

[108] JU Mehta, WA Borders, H Liu, R Pandey, S Datta, L Lunardi, "III–V tunnel FET model with closed-form analytical solution", IEEE Trans. Elec. Dev., vol. 63 no. 5, pp. 2163-2168, 2016.

[107] D Li, AA Sharma, DK Gala, N Shukla, H Paik, S Datta, DG Schlom, J. A Bain, M. Skowronski, "Joule Heating-Induced Metal–Insulator Transition in Epitaxial VO2/TiO2 Devices", ACS Appl. materials & interfaces, vol. 8 no. 20, pp. 12908-12914, 2016.

[106] K Majumdar, S Datta, SP Rao, "Revisiting the theory of ferroelectric negative capacitance", IEEE Trans. Elec. Dev., vol. 63 no. 5, pp. 2043-2049, 2016.

[105] W.-Y. Tsai, X. Li, M. Jerry, B. Xie, N. Shukla, H. Liu, N. Chandramoorthy, M. Cotter, A. Raychowdhury, D. M Chiarulli, S. P Levitan, S. Datta, J. Sampson, N. Ranganathan, and V. Narayanan, "Enabling new computation paradigms with hyperFET-an emerging device", IEEE Trans. on Multi-Scale Computing Sys., vol. 2, no. 1, pp. 30-48, 2016.

[104] A. Aziz, S. Ghosh, S. Datta and S. K. Gupta, "Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors," IEEE Elec. Dev. Lett., vol. 37, no. 6, pp. 805-808, June 2016.

[103] M. S. Kim, X. Li, H. Liu, J. Sampson, S. Datta, and V. Narayanan, “Exploration of low-power high-SFDR current-steering D/A converter design using steep-slope Heterojunction Tunnel FETs,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), VOL. 24, NO. 6, pp. 2299-2308, JUNE 2016.

[102] W.-Y. Tsai, X. Li, M. Jerry, B. Xie, N. Shukla, H. Liu, N. Chandramoorthy, M. Cotter, A. Raychowdhury, D. M. Chiarulli, S. P. Levitan, S. Datta, J. Sampson, N. Ranganathan, and V. Narayanan, “Enabling new computation paradigms with Hyper-FET – an emerging device,” IEEE Transactions on Multi-Scale Computing Systems (TMSCS), Vol 2, NO. 1, pp 30-48, Jan-Mar 2016.

[101] M. S. Kim, W. Cane-Wissing, X. Li, and J. Sampson, S. Datta, S. K. Gupta and V. Narayanan, “Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells” ACM Journal on Emerging Technologies in Computing Systems, Vol. 12, No. 4, Article 38, May 2016.

Conferences

[138] R. Pandey, C. Schulte-Braucks, R.N. Sajjad, M. Barth, R.K. Ghosh, B. Grisafe, P. Sharma, N. von den Driesch, A. Vohra, B. Rayner, R. Loo, S. Mantl, D. Buca, C.C. Yeh, C.H. Wu, W. Tsai, D. Antoniadis, S. Datta, "Performance benchmarking of p-type In 0.65 Ga 0.35 As/GaAs 0.4 Sb 0.6 and Ge/Ge 0.93 Sn 0.07 hetero-junction tunnel FETs", IEEE International Electron Devices Meeting (IEDM), 2016.

[137] N. Shukla, B. Grisafe, R. K. Ghosh, N. Jao, A. Aziz, J. Frougier, M. Jerry, S. Sonde, S. Rouvimov, T. Orlova, S. Gupta, S. Datta, "Ag/HfO 2 based threshold switch with extreme non-linearity for unipolar cross-point memory and steep-slope phase-FETs", IEEE International Electron Devices Meeting (IEDM), 2016.

[136] X. Yin, A. Aziz, J. Nahas, S. Datta, S. Gupta, M. Niemier, X.S. Hu, "Exploiting ferroelectric fets for low-power non-volatile logic-in-memory circuits", 35th International Conference on Computer-Aided Design, 2016.

[135] S. Datta, N. Shukla, "In quest of the next switch", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Nuremberg, Germany, 2016.

[134] R. K. Ghosh, S. Datta, "Orbitronics—Harnessing metal-insulator phase transition in 1T-MoSe2", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Nuremberg, Germany, 2016.

[133] D Wang, S George, A Aziz, S Datta, V Narayanan, SK Gupta, "Ferroelectric Transistor based Non-Volatile Flip-Flop", International Symposium on Low Power Electronics and Design (ISLPED), 2016.

[132] A Parihar, N Shukla, S Datta, A Raychowdhury, "Computing with dynamical systems in the post-CMOS era", IEEE Photonics Society Summer Topical Meeting Series (SUM), 2016.

[131] S George, A Aziz, X Li, MS Kim, S Datta, J Sampson, S Gupta, V. Narayanan, "Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors", IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.

[130] S Datta, "Transistor innovation in the 21st century—A lesson in serendipity", Device Research Conference (DRC), Delaware, USA, June 2016.

[129] S Datta, N Shukla, A Parihar, A Raychowdhury, "Computing with coupled dynamical systems" IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, June 2016.

[128] S Datta, R Pandey, S Mookerjea, "Opportunties and challenges of tunnel FETs", IEEE International Symposium on Circuits and Systems (ISCAS), Canada, May 2016.

[127] S. K. Gupta, A. Aziz, N. Shukla, S. Datta, "On the potential of correlated materials in the design of spin-based cross-point memories", IEEE International Symposium on Circuits and Systems (ISCAS), Canada, May 2016.

[126] R. Pandey, R. K. Ghosh, S. Datta,"Band structure engineered Germanium-Tin (GeSn) p-channel tunnel transistors", 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Taiwan, Apr. 2016.

[125] N. Shukla, S. Datta, A. Parihar, A. Raychowdhury, and V. Narayanan, "Computing with Coupled Dynamical Systems", CNNA 2016 - 15th International Workshop on Cellular Nanoscale Networks and their Applications, Dresden, Deutschland, Aug. 2016.

[124] N. Shukla, W.Y-. Tsai, M. Jerry, M. Barth, V. Narayanan, S. Datta, “Ultra-low powered coupled oscillators for computer vision applications” VLSI Symposium, Hawaii, June 2016.[PDF]

[123] N. Shukla, M. Jerry, H. Nair, M. Barth, D.G. Schlom, S. Datta, “Electrically Drive Reversible Insulator-Metal Phase Transition in Ca2RuO4”, Device Research Conference, June 2016.[PDF]

[122] J. Frougier, N. Shukla, D. Deng, M. J. Jerry, A. Aziz, L. Liu, G. Lavallee, T. S. Mayer, S. K. Gupta and S. Datta, “Phase-transition-FET Exhibiting Steep Switching Slope of 8mV/Decade and 36% Enhanced ON Current”, 2016 Symposia on VLSI Technology and Circuits, June 2016.

[121] A. Aziz, S. Ghosh, S. K. Gupta, and S. Datta,“Polarization Charge and Coercive Field Dependent Performance of Negative Capacitance FETs”, Device Research Conference (DRC) 2016, Delaware, USA.

[120] M. Jerry, N. Shukla, H. Paik, D. G. Schlom and S. Datta, "Dynamics of electrically driven sub-nanosecond switching in Vanadium dioxide",SiliconNanoelectrics Workshop (SNW), Honolulu HI, 2016.[PDF]

[119] M. Jerry, W. Tsai, B. Xie, X. Li, V. Narayanan, A. Raychodhury and S. Datta, "Phase Transition Oxide Neuron for Spiking Neural Networks" Device Research Conference (DRC), University of Delaware, 2016.[PDF]

[118] R Pandey, R. K. Ghosh, and S Datta, "Band structure engineered Germanium-Tin (GeSn) p-channel tunnel transistors", International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016.[PDF]

[117] M. J. Barth, A. Kumar, J. H. Warner, B. R. Bennett, J. B. Boos, C. D. Cress, N. J.-H. Roche, P. Paillet, M. Raine, M. Gaillardin, D. McMorrow, K. Saraswat, S. Datta “Single-Event Measurement and Analysis of Antimony-Based P-Channel Quantum-Well MOSFETs with High-k Dielectric” 2016 NSREC Portland OR, July 2016.

[116] S. George, K. Ma, A. Aziz, X. Li, A. Khan, S. Salahuddin, M.-F. Chang, S. Datta, J.Sampson, S. Gupta, V. Narayanan, “Nonvolatile Memory Design Based on Ferroelectric FETs”, Digital Automation Conference (DAC '16), June 05-09, 2016, Austin, TX, USA. DOI: http://dx.doi.org/10.1145/2897937.2898050

[115] D. Wang, S. George, A. Aziz, S. Datta, V. Narayanan and S. K. Gupta, “Ferroelectric Transistor Based Non-Volatile Flip-Flop”, Accepted in International Symposium on Low Power Electronics and Design (ISLPED), 2016.

[114] S. K Gupta, A. Aziz, N. Shukla and S. Datta, et al, “On the Potential of Correlated Materials in the Design of Spin-based Cross-point Memories (Invited)”, to be presented in IEEE International Symposium on Circuits and Systems (ISCAS), 2016, Montreal, Canada.

[113] S. George, A. Aziz, X. Li, M. S. Kim, J. Sampson, S. Datta, S. K. Gupta, V. Narayanan, “Device –Circuit Co Design of FEFET Based Logic for Low Voltage Processors”, Accepted in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2016.

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2015

Journals

[100] K. Martens, J. W. Jeong, N. Aetukuri, C. Rettner, N. Shukla, E. Freeman, D. N. Esfahani, F. M. Peeters, T. Topuria, P. M. Rice, A. Volodin, B. Douhard, W. Vandervorst, M. G. Samant, S. Datta, and S. S. P. Parkin, "Field Effectand Strongly Localized Carriers in the Metal-Insulator Transition Material VO2", Physical Review Letters, Nov 6, 2015.

[99] H. Paik, J. A. Moyer, T. Spila, J.W. Tashman, J. A. Mundy, E. Freeman, N.Shukla, J.M. Lapano, R. Engel-Herbert, W. Zander, J. Schubert, D.A. Muller, S. Datta, P. Schiffer, and D. G. Schlom, "Transport properties of ultra-thin VO2 films on (001) TiO2 grown by reactive molecular-beam epitaxy" Applied Physics Letters 106, 163101, Oct 19, 2015.

[98] Y. X. Zheng, A. Agrawal, G. B. Rayner, Jr., M. J. Barth, K. Ahmed, S. Datta, and R. Engel-Herbert "In Situ Process Control of Trilayer Gate-Stacks on p-Germanium With 0.85-nm EOT", IEEE Electron Device lett., vol. 36, no. 9, pp 881-883, Sep. 2015. [PDF]

[97] J. U. Mehta, W. A. Borders, H. Liu, R. Pandey, S. Datta, and L. Lunardi, "III–V Tunnel FET Model With Closed-Form Analytical Solution", IEEE Trans. Elec. Dev., vol. , no. , pp , Sept. 2015. [PDF]

[96] P. Maffezzoni, L. Daniel, N. Shukla, S. Datta, A. Raychowdhury, "Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators", IEEE Trans. Circuits and Systems, vol. 62, no. 9, pp 2207-2215, Sept. 2015. [PDF]

[95] P. Maffezzoni, L. Daniel, N. Shukla, S. Datta, A. Raychowdhury and V. Narayanan, "Modelling hysteresis in vanadium dioxide oscillators", IET Electron. Lett., vol. 51, pp 819-820, May 2015. [PDF]

[94] S. Dasgupta, A. Rajashekhar, K. Majumdar, N. Agrawal, A. Razavieh, S. Trolier-Mckinstry, and S. Datta, "Sub-kT/q Switching in Strong Inversion in PbZr0:52Ti0:48O3 Gated Negative Capacitance FETs", IEEE J. Exploratory Solid-State Comp. Dev. and Cir., vol. 1, pp 43-48, Aug. 2015. [PDF]

[93] N. Shukla, A. V. Thathachary, A. Agrawal, H. Paik, A. Aziz, D. G. Schlom, S. K. Gupta, R. Engel-Herbert and S. Datta, "A steep-slope transistor based on abrupt electronic phase transition", Nature Comm., vol. 6, pp 7812, Jun. 2015. [PDF]

[92] Y.-C. Lin, R. K. Ghosh, R. Addou, N. Lu, S. M. Eichfeld, H. Zhu, M.-Y. Li, X. Peng, M. J. Kim, L.-J. Li, R. M. Wallace, S. Datta, and J. A. Robinson, "Atomically thin resonant tunnel diodes built from synthetic van der Waals heterostructures", Nature Comm., vol. 6, pp 7311, Jun. 2015. [PDF]

[91] N. Agrawal, H. Liu, R. Arghavani, V. Narayanan, and S. Datta,, "Impact of Variation in Nanoscale Silicon and Non-Silicon FinFETs and Tunnel FETs on Device and SRAM Performance", IEEE Trans. Electron Devices, vol. 62, no. 6, pp 1691-1697, Jun. 2015. [PDF]

[90] L. Liu, X. Li, V. Narayanan, and S. Datta,, "A Reconfigurable Low-Power BDD Logic Architecture Using Ferroelectric Single-Electron Transistors", IEEE Trans. Electron Devices, vol. 62, no. 3, pp 1052-1057, Mar. 2015. [PDF]

[89] A. Parihar, N. Shukla, S. Datta, A. Raychowdhury, "Synchronization of pairwise-coupled, identical, relaxation oscillators based on metal-insulator phase transition devices: A Model Study", J. Appl. Phys. vol. 117, pp 054902 Feb. 2015. [PDF]

[88] M. J. Hollander, Y. Liu, W-J. Lu, L-J. Li, Y-P. Sun, J. A. Robinson, and S. Datta, "Electrically Driven Reversible Insulator–Metal Phase Transition in 1T-TaS2", NanoLetters 15(3), pp 1861-1866, Jan. 2015. [PDF]

[87] H. Madan, M. Jerry, A. Pogrebnyakov, T. Mayer, and S. Datta, "Quantitative Mapping of Phase Coexistence in Mott-Peierls Insulator during Electronic and Thermally Driven Phase Transition", ACS Nano 9(2), pp 2009-2017, Jan. 2015. [PDF]

[86] A. V. Thathachary, G. Lavallee, M. Cantoro, K. K. Bhuwalka, Y-C. Heo, S. Maeda, and S. Datta, "Impact of Sidewall Passivation and Channel Composition on InxGa1-xAs FinFET Performance", IEEE Electron Device lett., vol. 36, no. 2, pp 117-119, Feb. 2015. [PDF]

[85] N. Agrawal, A. V. Thathachary, S. Mahapatra, and S. Datta, "Impact of Varying Indium(x) Concentration and Quantum Confinement on PBTI Reliability in InxGa1-xAs FinFET", IEEE Electron Device lett., vol. 36, no. 2, pp 120-122, Feb. 2015. [PDF]

[84] B. Rajamohanan, R. Pandey, V. Chobpattana, C. Vaz, D. Gundlach, K. P. Cheung, J. Suehle, S. Stemmer, and Suman Datta, "0.5 V Supply Voltage Operation of In0.65Ga0.35As/GaAs0.4Sb0.6 Tunnel FET", IEEE Electron Device lett., vol. 36, no. 1, pp 20-22, Jan. 2015. [PDF]

Conferences

[112] R Pandey, N Agrawal, V Chobpattana, K Henry, M Kuhn, H Liu, M Labella, C. Eichfeld, K. Wang, J. Maier, S. Stemmer, S. Mahapatra, S. Datta "Tunnel junction abruptness, source random dopant fluctuation and PBTI induced variability analysis of GaAs0. 4Sb0. 6/In0. 65Ga0. 35As heterojunction tunnel FETs" 2015 IEEE International Electron Devices Meeting (IEDM), pp. 14.2. 1-14.2. 4  2015

[111] H Madan, HT Zhang, M Jerry, D Mukherjee, N Alem, R Engel-Herbert, S Datta "26.5 Terahertz electrically triggered RF switch on epitaxial VO2-on-Sapphire (VOS) wafer" 2015 IEEE International Electron Devices Meeting (IEDM), pp. 9.3. 1-9.3. 4  2015

 [110] Trivedi, R Pandey, H Liu, S Datta, S Mukhopadhyay "Gate/Source overlapped heterojunction tunnel FET for non-Boolean associative processing with plasticity" 2015 IEEE International Electron Devices Meeting (IEDM), pp. 17.8. 1-17.8. 4     2015

[109] A. Aziz, N. Shukla, S. Datta and S. K Gupta, “Implication of Hysteretic Selector Device on the Biasing Scheme of a Cross-point Memory Array”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Washington DC, USA.

[108] Ram Krishna Ghosh, Yu-Chuan Lin, Joshua A. Robinson and Suman Datta “Heterojunction resonant tunneling diode at the atomic limit”, International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2015, Washington DC, USA

[107] A. Aziz, N. Shukla, S. Datta and S. K Gupta, “COAST: Correlated Material Assisted STT MRAMs for Optimized Read Operation”, International Symposium on Low Power Electronics and Design (ISLPED), 2015, Rome, Italy

[106] M. Barth, H. Liu, J. H. Warner, B. R. Bennett, D. McMorrow, N. Roche, P. Paillet, M. Gaillardin, and S. Datta "Single Event Measurement and Analysis of Antimony based n-channel Quantum-Well MOSFET with High-k Dielectric" 2015 NSREC Boston MA, July 2015

[105] M. Barth, G. Bruce Rayner, R. Engel-Herbert, and S. Datta "Preparation of high quality high-?/GaSb interfaces using in-situ spectroscopic ellipsometry and reflection high energy electron diffraction" 2015 AVS ALD Conference, Portland OR June 2015

[104] R. Pandey, H. Madan, H. Liu, V. Chobpattana, M. Barth, B. Rajamohanan, M. J. Hollander, T. Clark, K. Wang, J- H. Kim, D. Gundlach, K. P. Cheung, J. Suehle, R. Engel-Herbert, S. Stemmer and S. Datta, "Demonstration of p-type In0.7Ga0.3As/GaAs0.35Sb0.65 and n-type GaAs0.4Sb0.6/In0.65Ga0.35As Complimentary Heterojunction Vertical Tunnel FETs for Ultra-Low Power Logic", IEEE Symposia on VLSI Technology and Circuits, Kyoto, 2015. [PDF]

[103] A. V. Thathachary, N. Agrawal, K. K. Bhuwalka, M. Cantoro, Y-C Heo, G. Lavallee, S. Maeda, and S. Datta, "Indium Arsenide (InAs) Single and Dual Quantum-Well Heterostructure FinFETs", IEEE Symposia on VLSI Technology and Circuits, Kyoto, 2015. [PDF]

[102] A. Aziz, N. Shukla, S. Datta and S. K. Gupta, "Read Optimized MRAM with Separate Read-Write Paths based on Concerted Operation of Magnetic Tunnel Junction with Correlated Material", Device Research Conference (DRC), Ohio State University, 2015. [PDF]

[101] R. Pandey, N. Agrawal, R. Arghavani, and S. Datta, "Analysis of Local Interconnect Resistance at Scaled Process Nodes", Device Research Conference (DRC), Ohio State University, 2015. [PDF]

[100] N. Agrawal, A. Agrawal, S. Mukhopadhyay, S. Mahapatra, and S. Datta, "Electron Trapping Dominance in Strained Germanium Quantum Well Planar and FinFET devices with NBTI", Device Research Conference (DRC), Ohio State University, 2015. [PDF]

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2014

Journals

[83] M. Barth, G. B. Rayner, S McDonnell, R.M. Wallace, B.R. Bennett, R. Engel-Herbert, and S. Datta, "High quality HfO2/p-GaSb(001) metal-oxide-semiconductor capacitors with 0.8nm equivalent oxide thickness", Applied Physics Letters 105, 222103, Dec 2, 2014. [PDF]

[82] A.Parihar, N. Shukla, S. Datta, A. Raychowdhury, "Exploiting Synchronization Properties of Correlated Electron Devices in a Non-Boolean Computing Fabric for Template Matching", The IEEE Journal on Emerging and Selected Topics in Circuits and Systems, pp 1, October 2014", October 2014. [PDF]

[81] Yu-C. Lin, C-Y. S. Chang, R. K. Ghosh, J. Li, H. Zhu, R. Addou, B. Diaconescu, T. Ohta, X. Peng, Ning Lu, M. J. Kim, J. T. Robinson, R. M Wallace, T. S. Mayer, S. Datta, L-J. Li, and J. A. Robinson, "Atomically Thin Heterostructures Based on Single-Layer Tungsten Diselenide and Graphene", NanoLetters 14(12), pp 6936-6941, Nov. 2014. [PDF]

[80] W. Li, Q. Zhang, R. Bijesh, O.A. Kirillov, Y. Liang, I. Levin, Lian-Mao Peng, C. A. Richter, X. Liang, S. Datta, D. J. Gundlach, and N. V. Nguyen "Electron and hole photoemission detection for band offset determination of tunnel field-effect transistor heterojunctions", Applied Physics Letters 105, 213501, November 10, 2014. [PDF]

[79] M. S. Kim, H. Liu, X. Li, S. Datta, and V. Narayanan, "A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter", IEEE Transactions on Electron Devices, vol. 61, no.11, pp: 3661-3666, November 2014. [PDF]

[78] X. Li, H. Liu*, S. Datta, R. Vaddi, V.Narayanan, K. Ma, “Tunnel FET RF Rectifier Design for Energy Harvesting Application”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol 4, no 4, pp 400-411, October 2014 (Second author supervised by the candidate)

[77] A. R. Trivedi, S. Datta, Fellow, and S. Mukhopadhyay "Application of Silicon-Germanium Source Tunnel-FET to Enable Ultralow Power Cellular Neural Network-Based Associative Memorys", IEEE Transactions on Electron Devices, vol. 61, no.11, pp: 3707-3715, November 2014. [PDF]

[76] M. Huefner, R. K. Ghosh, E. Freeman, N. Shulka, H. Paik, D. G. Schlom, and S. Datta "Hubbard Gap Modulation in Vanadium Dioxide Nanoscale Tunnel Junctions", Nano Letters, October 2014. [PDF]

[75] A. Agrawal, M. Barth, H. Madan, Yi-Jing Lee, You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, C. H. Wann, D. Loubychev, A. Liu, J. Fastenau, J. Lindemuth, and S. Datta "Comparative analysis of hole transport in compressively strained InSb and Ge quantum well heterostructures", Applied Physics Letters 105, 052102, August 5, 2014. [PDF]

[74] N. Shukla, T. Joshi, S. Dasgupta, P. Borisov, D. Lederman, and S. Datta "Electrically induced insulator to metal transition in epitaxial SmNiO3 thin films", Applied Physics Letters 105, 012108, July 11, 2014. [PDF]

[73] H. Liu, M. Cotter, S. Datta, and V. Narayanan, "Soft-Error Performance Evaluation on Emerging Low Power Devices", IEEE Transactions on Device and Materials Reliability, vol. 14, no. 2, June 3, 2014. [PDF]

[72] N. Shukla, A. Parihar, E. Freeman, H. Paik, G. Stone, V. Narayanan, H. Wen, Z. Cai, V. Gopalan, R. Engel-Herbert, D. G. Schlom, A. Raychowdhury, and S. Datta "Synchronized charge oscillations in correlated electron systems", Scientific Reports 4:4964, May 14, 2014 [PDF]

[71] A. Agrawal, J. Lin, M. Barth, R.White, B. Zheng, S. Chopra, S. Gupta, K. Wang, J.Gelatos, S. Mohney, and S. Datta "Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts", Applied Physics Letters Vol.104, 112101, March 17, 2014. [PDF]

[70] M. Hollander, H. Madan, N. Shukla, D. Snyder, J. Robinson, and S. Datta, "Short-channel graphene nanoribbon transistors with enhanced symmetry between p- and n-branches", Appl. Phys. Express, 7, 055103 (2014). [PDF]

[69] R. Pandey, V. Saripalli, J.P. Kulkarni, V. Narayanan, and S. Datta, "Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability ", IEEE Electron Device Letters Vol. 35. NO. 3, March 2014 [PDF]

[68] S Datta, H. Liu, and V. Narayana "Tunnel FET technology: A reliability perspective", Microelectronics Reliability, March 3, 2014. [PDF]

[67] R. Pandey, B. Rajamohanan, H. Liu,V. Narayanan, and S. Datta, "Electrical Noise in Heterojunction Interband Tunnel FETs", IEEE Transactions on Electron Devices, vol. 61, no.2, pp: 552-559, February 2014. [PDF]

[66] A. V. Thathachary, N. Agrawal, L. Liu, and S. Datta, "Electron Transport in Multigate InxGa1-x As Nanowire FETs: From Diffusive to Ballistic Regimes at Room Temperature", Nano Letters 2014 Feb 12;14(2):626-33. [PDF]

[65] B. Rajamohanan, D. Mohata, Y. Zhu, M. Hudait, Z. Jiang, M. Hollander, G. Klimeck, and S. Datta "Design, fabrication, and analysis of p-channel arsenide/antimonide hetero-junction tunnel transistors" J. Appl. Phys. 115, 044502. January 2014 [PDF]

Conferences

[99] A. Agrawal, M. Barth, G. B. Rayner Jr., Arun V. T., C. Eichfeld, G. Lavallee, S-Y. Yu, X. Sang, S. Brookes, Y. Zheng, Y-J. Lee, Y-R. Lin, C-H. Wu, C-H. Ko, J. LeBeau, R. Engel-Herbert1, S. E. Mohney, Y-C. Yeo and S. Datta "Enhancement Mode Strained (1.3%) Germanium Quantum Well FinFET (WFin=20nm) with High Mobility (Hole=700 cm2/Vs), Low EOT (~0.7nm) on Bulk Silicon Substrate", IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 414-417, December 2014 [PDF] [Presentation]

[98] N. Shukla, A. Parihar, M. Cotter, M. Barth, X. Li, N. Chandramoorthy, H. Paik, D. G. Schlom, V. Narayanan, A. Raychowdhury and S. Datta, "Pairwise Coupled Hybrid Vanadium Dioxide-MOSFET (HVFET) Oscillators for Non-Boolean Associative Computing", IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 673-676, December 2014 [PDF] [Presentation]

[97] Moon Seok Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman Datta, Vijaykrishnan Narayanan "Enabling power-efficient designs with III-V Tunnel FETs" The IEEE Compound Semiconductor IC Symposium (CSICS), October, 2014. [PDF]

[96] Matthew J. Hollander, Himanshu Madan, Gregory Pastir, Randal Cavalero, David Snyder, Joshua A. Robinson, and Suman Datta. "Enhanced Short-channel Performance and p-n Symmetry in Graphene Based Ambipolar Mixer Using Nano-ribbon Geometry" 4th International Symposium on Graphene Devices, Sept. 2014

[95] H. Liu, M. Shoaran, X. Li, S.Datta, A.Schmid, and V. Narayanan "Tunnel FET-Based Ultra-Low Power, Low-Noise Amplifier Design for Bio-signal Acquisition" International Symposium on Low Power Electronics and Design, La Jolla, CA, USA, August, 2014. [PDF]

[94] Datta, S. , Pandey, R. ; Agrawal, A. ; Gupta, S.K. ; Arghavani, R. "Impact of contact and local interconnect scaling on logic performance " IEEE Symposia on VLSI Technology, Honolulu, June, 2014. [PDF] (Invited Paper)[91] Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Don Chiarulli, Steve Levitan,and Philip Wong, "Video Analytics Using Beyond CMOS Devices", Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 March 2014 [PDF]

[93] Thathachary, Arun V., Agrawal, N., Lavallee G.,Cantoro M.,Kim Sang-Su,kim Dong-Won and Datta S. "Investigation of InxGa1-xAs FinFET architecture with varying Indium (x) concentration and quantum connement" IEEE Symposia on VLSI Technology, Honolulu, June, 2014. [PDF]

[92] Suman Datta, Nikhil Shukla, Matthew Cotter, Abhinav Parihar, Arijit Raychowdhury, "Neuro Inspired Computing with Coupled Relaxation Oscillators", Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference (DAC), pp 1-6, June 2014 (Invited Paper)

[91] Vijaykrishnan Narayanan, Suman Datta, Gert Cauwenberghs, Don Chiarulli, Steve Levitan, and Philip Wong, "Video Analytics Using Beyond CMOS Devices", Design, Automation and Test in Europe Conference and Exhibition (DATE), March 2014 (equal contribution by all authors) (invited talk)

[90] Chian-We Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen§, Suman Datta, Vijaykrishnan Narayanan, "Width Minimization in the Single-Electron Transistor Array Synthesis", Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 March 2014 [PDF]

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2013

Journals

[64] E. Freeman, G Stone, N. Shukla, H. Paik, J. A. Moyer, Z. Cai,H. Wen, R. Engel-Herbert, D. G. Schlom V. Gopalan, and S. Datta "Nanoscale structural evolution of electrically driven insulator to metal transition in vanadium dioxide", in Applied Physics Letters Vol.103, Issue 26 December 30, 2013. [PDF]

[63] N. Agrawal, Y, Kimura, R. Arghavani, and S. Datta, "Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III Semiconductor) on Variation for Logic and SRAM Applications", IEEE Transactions on Electron Devices, vol. 60, no.10, pp: 3298-3304, October 2013. [PDF]

[62] B. Rajamohanan, D. Mohata, D. Zhernokletov, B. Brennan, R. M. Wallace, R. Engel-Herbert, and S. Datta, "Low-Temperature Atomic-Layer-Deposited High-k Dielectric for p-Channel In0.7Ga0.3As/GaAs0.35Sb0.65 Heterojunction Tunneling Field-Effect Transistor", Appl. Phys. Express, 6, 101201 (2013). [PDF]

[62] Lubyshev, Joel M. Fastenau, and Amy K. Liu "Structural, morphological, and defect properties of metamorphic In0.7Ga0.3As/GaAs0.35Sb0.65 p-type tunnel field effect transistor structure grown by molecular beam epitaxy" Journal of Vacuum Science and Technology B 31(4), pp 041203-1, Jul/Aug 2013 (Third author supervised by the candidate)

[61] C. Cress and S. Datta, "Nanoscale transistor – Just around the gate", Science, vol. 341, pp. 140-141 (2013) [PDF]

[61] R. Bijesh, D. Mohata, A. Ali, and Suman Datta "Insight into the output characteristics of III-V tunneling field effect transistors " Appl. Phys. Lett. 102, 092105 March 2013 [PDF]

[60] A Ali, H. Madan, M. Barth, J. B. Boos, B. R. Bennett, and S. Datta "Effect of Interface States on the Performance of Antimonide nMOSFETs" IEEE Electron Device Letters Vol. 34. NO. 3, March 2013 [PDF]

[59] YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V. Narayanan "A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays" CM Journal on Emerging Technologies in Computing Systems (JETC) Volume 9 Issue 1, February 2013 Article No. 5 [PDF]

[58] Ayan Kar, Nikhil Shukla, Eugene Freeman, Hanjong Paik, Huichu Liu, Roman Engel-Herbert,S. S. N. Bhardwaja, Darrell G. Schlom, and Suman Datta "Intrinsic electronic switching time in ultrathin epitaxial vanadium dioxide thin film" Appl. Phys. Lett. 102, 072106 February 2013 [PDF]

[57] L. Liu, V. Narayanan, and S.Datta "A programmable ferroelectric single electron transistor" Appl. Phys. Lett. 102, 053505 February 2013 [PDF]

[56] Y. Zhu, N. Jain, S. Vijayaraghavan, D. K. Mohata, S. Datta, D. Lubyshev, J. M. Fastenau, A. K. Liu, , and M. K. Hudait "Band offset determination of mixed As/Sb type-II staggered gap heterostructure for n-channel tunnel field effect transistor application" J. Appl. Phys. 113, 024319 January 2013 [PDF]

Conferences

[89] R. Bijesh, H. Liu, H. Madan, D. Mohata, W. Li, N. V. Nguyen, D. Gundlach , C.A. Richter, J. Maier, K. Wang, T. Clarke, J. M. Fastenau, D. Loubychev, W. K. Liu, V. Narayanan and S. Datta, "Demonstration of InGaAs/GaAsSb Near Broken-gap Tunnel FET with Ion=740uA/um, Gm=700uS/um and Gigahertz Switching Performance at VDS=0.5V", IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 687-690, December 2013 [PDF]

[88] H. Liu, S. Datta, and V. Narayanan "Steep Switching Tunnel FET: A Promise to Extend the Energy Efficient Roadmap for Post-CMOS Digital and Analog/RF Application" International Symposium on Low Power Electronics and Design (ISLPED) Beijing, China, September 4-6, 2013 [PDF]

[87] H. Liu, R. Vaddi, S. Datta, and V. Narayanan "Tunnel FET based Ultra-Low Power, High Sensitivity UHF RFID Rectifier" at International Symposium on Low Power Electronics and Design (ISLPED) Beijing, China, September 4-6, 2013 [PDF]

[86] M. Barth, A. Agrawal, A. Ali, J. Fastenau, D. Loubychev, W.K. Liu and S.Datta "Compressively Strained InSb MOSFETs with High Hole Mobility for P-Channel Application" Device Research Conference (DRC),University of Notre Dame, June 23-26, 2013. [PDF]

[85] Arun V. Thathachary, L. Liu and S.Datta "Impact of fin width scaling on carrier transport in III-V FinFETs" Device Research Conference (DRC),University of Notre Dame, June 23-26, 2013. [PDF]

[84] Matthew J. Hollander, Nikhil Shukla, Nidhi Agrawal, Himanshu Madan, Joshua A. Robinson and Suman Datta "Reduction of Charge Transfer Region Using Graphene Nano-ribbon Geometry for Improved Complementary FET Performance at Sub-Micron Channel Length" Device Research Conference (DRC),University of Notre Dame, June 23-26, 2013. [PDF]

[83] H. Madan, M. J. Hollander, J. A. Robinson, and S. Datta "Analysis and Benchmarking of Graphene Based RF Low Noise Amplifiers " Device Research Conference (DRC),University of Notre Dame, June 23-26, 2013. [PDF]

[82] A. Agrawal, J. Lin, B. Zheng, S. Sharma, S. Chopra, K. Wang, A. Gelatos, S. Mohneyand S. Datta "Barrier Height Reduction to 0.15eV and Contact Resistivity Reduction to 9.1×10-9 ?-cm2 Using Ultrathin TiO2-x Interlayer between Metal and Silicon" 2013 VLSI Symposia,Kyoto, Japan, June 11-14, 2013. [PDF]

[81] H. Madan, M. J. Hollander, J. A. Robinson and S. Datta "Graphene Transistors for Ambipolar Mixing at Microwave Frequencies" 223rd Electrochemical Society Meeting, Toronto, ON, Canada May 14-18 2013 [PDF]

[80] S. Datta, R. Bijesh, H. Liu, D. Mohata, and V. Narayanan "Tunnel Transistors for Energy Efficent Computing" IEEE International Reliability Physics Symposium (IRPS),Monterey, California, April 14- 18 2013 [PDF]

[79] K. Joshi, S. Hung, S. Mukhopadhyay, V. Chaudhary, N. Nanaware, B. Rajamohnan,T. Sato, M. Bevan, A. Wei, A. Noori, B. Mc.Dougal,C. Ni,G. Saheli, C. Lazik, P. Liu, D. Chu, L. Date, S. Datta, A. Brand, J Swenberg, and S. Mahapatra "HKMG Process Impact on N, P BTI: Role of Thermal IL Scaling, IL/HK Integration and Post HK Nitridationg" IEEE International Reliability Physics Symposium (IRPS),Monterey, California, April 14- 18 2013 [PDF]

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2012

Journals

[55] S. K. Gupta, J. P Kulkarni, S. Datta and K. Roy, "Heterojunction Intra-band Tunneling (HIBT) FETs for Low Voltage SRAMs" IEEE Transactions on Electron Devices, vol. 59, no.12, pp: 3533-3542, December 2012. [PDF]

[54] Y. Zhu, N. Jain, S. Vijayaraghavan, D. K. Mohata, S. Datta, D. Lubyshev, J. M. Fastenau,A. K. Liu, N. Monsegue, and M. K. Hudait "Defect assistant band alignment transition from staggered to broken gap in mixed As/Sb tunnel field effect transistor heterostructure" J. Appl. Phys. 122, 094312 October 2012. [PDF]

[53] H. Madan, V. Saripalli, H. Liu, and S. Datta, "Asymmetric Tunnel Field-Effect Transistors as Frequency Multipliers" IEEE Electron Device Lettersvol. 33, no. 11, pp. 1547-1549, November 2012. [PDF]

[52] D. K. Mohata, R. Bijesh, T. Mayer, J. Fastenau, D. Lubyshev, A. W. K. Liu, and S. Datta, "Barrier Engineered Arsenide-Antimonide Hetero-junction Tunnel FETs with Enhanced Drive Current" IEEE Electron Device Letters vol. 33, no. 11, pp. 1568-1570, November 2012. [PDF]

[51] J. D. Yearsley, J. C. Lin, E. Hwang, S. Datta, and S. E. Mohney "Ultra low-resistance palladium silicide Ohmic contacts to lightly doped n-InGaAs" J. Appl. Phys. 112, 054510, September 2012 [PDF]

[50] Y. Zhu, N. Jain, D. K. Mohata, S. Datta, D. Lubyshev, J. M. Fastenau,A. K. Liu, and M. K. Hudait "Structural properties and band offset determination of p-channel mixed As/Sb type-II staggered gap tunnel field-effect transistor structure" Appl. Phys. Lett. 101, 112106 September 2012. [PDF]

[49] R. Bijesh, I.Ok, S. Mujumdar, C. Hobbs, P. Majhi, R. Janmmy, and S.Datta, "Correlated Flicker Noise and Hole Mobility Characteristics of (110)/<110> Uniaxially Strained SiGe FINFETs" IEEE Electron Device Letters, vol. 33, no. 09, pp. 1237-1239, September 2012. [PDF]

[48] F. Li, R. Misra, Zhao Fang, Y. Wu, P. Schiffer, Q. M. Zhang, S. Tadigadapa and S. Datta, "Magnetoelectric Flexural Gate Transistor with NanoTesla Sensitivity" Journal of MEMS, Aug 2012. [PDF]

[47] Y. Zhu, N. Jain, S. Vijayaraghavan, D. K. Mohata, S. Datta, D. Lubyshev, J. M. Fastenau, W. K. Liu, N. Monsegue, and M. K. Hudait, "Role of InAs and GaAs terminated heterointerfaces at source/channel on the mixed As-Sb staggered gap tunnel field effect transistor structures grown by molecular beam epitaxy" Journal of Applied Physics, 112, 024306 July 2012. [PDF]

[46] A. Agrawal, N. Shukla, K. Ahmed, and S.Datta, "A Unifed Model for Insulator Selection to Form Ultra-Low Resistivity Metal-Insulator-Semiconductor Contacts to n-Si, n-Ge and n-InGaAs" Applied Physics Letters,101, 042108, July 2012. [PDF]

[45] L. Liu, D. K. Mohata, and S. Datta, "Scaling Length Theory of Double-Gate Interband Tunnel Field-Effect Transistors" IEEE Transactions on Electron Devices,59(4), pp. 902-908, April 2012. [PDF]

[44] W. Cho, M. Luisier, D. K. Mohata, S. Datta, D. Pawlik, S. L. Rommel, and G. Klimeck "Full band atomistic modeling of homo-junction InGaAs band-to-band tunneling diodes including band gap narrowing" Applied Physics Letters,100(6), pp. 063504 - 063504-3 ,February 2012. [PDF]

[43] S. Mujumdar, K. Maitra, and S. Datta "Layout dependent strain optimization for p-channel Non-planar Tri-gate Transistors" IEEE Transactions on Electron Devices, 59(1), pp. 72-78,January 2012. [PDF]

Conferences

[78] H. Madan, M.J. Hollander, M. LaBella, R. Cavalero, D. Snyder, J. A. Robinson and S. Datta, "Record High Conversion Gain Ambipolar Graphene Mixer at 10 GHz Using Scaled Gate Oxide", IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 76-79, December (2012) [PDF]

[77] Huichu Liu, Matthew Cotter, Suman Datta and Vijay Narayanan, "Technology Assessment of Si and III-V FinFETs and III-V Tunnel FETs from Soft Error Rate Perspective", IEEE International Electron Device Meeting (IEDM) Technical Digest, pp. 577-580, December (2012). [PDF]

[76] E. Kultursay , K. Swaminathan , V. Saripalli, S. Datta , V. Narayanan, and M. Kandemir, "Performance Enhancement under Power Constraints using Heterogeneous CMOS-TFET Multicores" accepted at IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, Oct 7-12, 2012. [PDF]

[75] R. Mukundrajan, M. Cotter, V. Saripalli, M. J. Irwin, S. Datta, and V. Narayanan, "Ultra Low Power Circuit Design using Tunnel FETs" 11th IEEE Computer Society Annual Symposium on VLSI (ISVLSI2012), , Aug 19 ¨C 21, Amherst, USA. [PDF]

[74] M. J. Hollander, A. Agrawal, M. S. Bresnehan, M. LaBella, K. A. Trumbull, R. Cavalero, S. Datta, and Joshua A. Robinson, "High Performance, Large Area Graphene Transistors on Quasi-Free- Standing Graphene Using Synthetic Hexagonal Boron Nitride Gate Dielectrics" Device REsearch Conference (DRC), Penn State University, June 18-20, 2012. [PDF]

[73] M. J. Hollander, A. Agrawal, M. S. Bresnehan, M. LaBella, K. A. Trumbull, R. Cavalero, S. Datta, and Joshua A. Robinson, "Effect of Transferred Hexagonal Boron Nitride Dielectrics on Quasi-Freestanding Epitaxial Graphene" Electronic Materials Conference (EMC), Penn State University, June 18-20, 2012. [PDF]

[72] H. Liu, D. K. Mohata, A. Nidhi, V. Saripalli, V. Narayanan and S. Datta, "Exploration of Vertical MOSFET and Tunnel FET Device Architecture for Sub 10nm Node Applications" Device REsearch Conference (DRC), Penn State University, June 18-20, 2012. [PDF]

[71] H. Madan, M. J. Hollander, J. A. Robinson, and S. Datta, "Extraction of Near Interface Trap Density in Top Gated Graphene Transistor Using High Frequency Current Voltage Characteristics" Device REsearch Conference (DRC), Penn State University, June 18-20, 2012. [PDF]

[70] A. Agrawal, J. Park, D. K. Mohata, K. Ahmed, and S.Datta, "Experimental Demonstration of "Cold" Low Contact Resistivity Ohmic Contacts on Moderately Doped n-Ge with in-situ Atomic Hydrogen Clean" Device REsearch Conference (DRC), Penn State University, June 18-20, 2012. [PDF]

[69] E. Freeman, A. Kar, N. Shukla, R. Misra, R. Engel-Herbert, D. Schlom, V. Gopalan, K. Rabe, and S.Datta, "Characterization and Modeling of Metal-Insulator Transition (MIT) Based Tunnel Junctions" Device REsearch Conference (DRC), Penn State University, June 18-20, 2012. [PDF]

[68] N. Agrawal, V.Saripalli, V.Narayanan, Y.Kimura, R.Arghavani, and S.Datta, "Will Strong Quantum Confinement Effect Limit Low Vcc Applications of III-V FinFETs?" Device REsearch Conference (DRC), Penn State University, June 18-20, 2012. [PDF]

[67] R.Bijesh, D. K. Mohata, H. Liu, and S.Datta, "Flicker Noise Characterization and Analytical Modeling of Homo and Hetero-Junction III-V Tunnel FETs" Device Research Conference (DRC), Penn State University, June 18-20, 2012. [PDF]

[66] A. Ali, H. Madan, M. J. Barth, M. J. Hollander, J. B. Boos, B. R. Bennett, and S.Datta, "Antimonide NMOSFET with Source Side Injection Velocity of 2.7x107 cm/s for Low Power High Performance Logic Applications" IEEE Symposia on VLSI Technology and Circuits, Honolulu, June 12-15, 2012. [PDF]

[65] D. K. Mohata, R. Bijesh, Y. Zhu, M. K. Hudait, R. Southwick, Z. Chbili, D. Gundlach, J. Suehle, J. M. Fastenau, D. Loubychev, A. K. Liu, T. S. Mayer, V. Narayanan and S. Datta, "Demonstration of Improved Heteroepitaxy, Scaled Gate Stack and Reduced Interface States Enabling Heterojunction Tunnel FETs with High Drive Current and High On-Off Ratio" IEEE Symposia on VLSI Technology and Circuits, Honolulu, June 12-15, 2012. [PDF]

[64] K. Ahmeda , S. Chopraa, A. Agrawal and S. Datta "Benchmarking of Novel Contact Architectures on Silicon and Germanium" 2012 InternationalSilicon-Germanium Technology and Device Meeting (ISTDM), June 4-6 2012 [PDF]

[63] F. Li, R. Misra, Z. Fang, C. Curwen, Y. Wu, Q. M. Zhang, P. Schiffer, S. Tadigadapa, and S. Datta, "Magnetoelectric Resonant Gate Transistor" Solid-State Sensors, Actuators, and Microsystems Workshop, Hilton Head, June 3-7, 2012. [PDF]

[62] K. Ahmed, A. Agrawal, S. Chopra, and S. Datta, "Benchmarking of Novel Contact Architectures on Silicon and Germanium" International Silicon-Germanium Technology and Device Meeting (ISTDM), June 4, 2012. [PDF]

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2011

Journals

[42] A. Ali, H. Madan, A. Agrawal, I. Ramirez, R. Misra, J. B. Boos, B. R. Bennett, J. Lindemuth and S. Datta, "Enhancement Mode Antimonide Quantum Well MOSFETs with High Electron Mobility and GHz Small-Signal Switching Performance," IEEE Electron Device Letters, September 2011.[PDF]

[41] Matthew J Hollander, Michael LaBella, Zachary R Hughes, Michael Zhu, Kathleen A Trumbull, Randal Cavalero, David W Snyder, Xiaojun Wang, Euichul Hwang, Suman Datta, and Joshua A Robinson, "Enhanced Transport and Transistor Performance with Oxide Seeded High-k Gate Dielectrics on Wafer-Scale Epitaxial Graphene," Nano Letters, p. 110804163939013, Aug. 2011. [PDF]

[40] Vinay Saripalli, Guangyu Sun, Asit Mishra, Yuan Xie, Suman Datta and Vijaykrishnan Narayanan, "Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, June 2011. (Invited paper) [PDF]

[39] E.Hwang, S.Mookerjea, M.K Hudait, S.Datta, "Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for logic applications," Solid-State Electronics, vol. 62, pp. 82-89, August 2011. [PDF]

[38] D. Mohata, S. Mookerjea, A. Agrawal, Y. Li, T. Mayer, V. narayanan, A. Liu and S. Datta, "Experimental Staggered-Source and N+ Pocket-Doped Channel III-V Tunnel Field-Effect Transistors and Their Scalabilities," Applied Physics Express, vol 4, pp. 024105, February 2011. [PDF]

[37] A. Ali, B. Bennett, B. Boos, H. Madan, A. Agrawal, P. Schiffer, R. Misra and S. Datta, , "Experimental Determination of Quantum and Centroid Capacitance in Arsenide-Antimonide Quantum-Well MOSFETs Incorporating Non-Parabolicity Effect," IEEE Transactions on Electron Devices , vol. 58 , pp. 1397-1403, January 2011. [PDF]

[36] L. Liu* and S. Datta, “A Generalized Scaling Length Theory for Double Gate Inter-band Tunnel FETs,” accepted for publication in IEEE Transactions on Electron Devices, number of pages: 6, Dec 2011 (first author supervised by the candidate)

Conferences

[61] D. K. Mohata, R. Bijesh , S. Mujumdar, C. Eaton, R. Engel-Herbert, T. Mayer, V. Narayanan, J. Fastenau, D. Loubychev, A. Liu and S. Datta, "Demonstration of MOSFET-Like On-Current Performance in Arsenide/Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications", accepted IEEE International Electron Devices Meeting, Washington DC, Dec. 5-7, 2011

[60] L. Liu, V. Saripalli, V. Narayanan and S. Datta, "Device Circuit Co-Design Using Classical and Non-Classical III-V Multi-Gate Quantum-Well FETs (MuQFETs)", accepted IEEE International Electron Devices Meeting, Washington DC, Dec. 5-7, 2011

[59] V. Saripalli, J. P. Kulkarni, N. Vijaykrishnan and S. Datta, "Variation-Tolerant Ultra Low- Power Heterojunction Tunnel FET SRAM Design",IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), San Diego, CA, June 2011[PDF]

[58] A. Agrawal, A. Ali, R. Misra, P. E. Schiffer, J. B. Boos, B. R. Bennett and S. Datta, "Low Field Electron Transport in Mixed Arsenide Antimonide Quantum Well Heterostructures", Electronic Materials Conference (EMC), Univ. of California, Santa Barbara, June 2011 [PDF]

[57] A. Agrawal, A. Ali, R. Misra, P. E. Schiffer, B. R. Bennett, J. B. Boos and S. Datta, "Experimental Determination of Dominant Scattering Mechanisms in Scaled InAsSb Quantum Well", Device Research Conference (DRC), Univ. of California, Santa Barbara, pp. 27-28, June 2011 [PDF]

[56] R. Bijesh, I. OK, M. Baykan, C. Hobbs, P.Majhi, R.Jammy and S.Datta, "Hole Mobility Enhancement in Uniaxially Strained SiGe FINFETs: Analysis and Prospects", Device Research Conference (DRC), Univ. of California, Santa Barbara, pp. 237-238, June 2011 [PDF]

[55] D. K. Mohata, R. Bijesh, V. Saripalli, T. Mayer and S. Datta,” Self-aligned Gate NanoPillar In0.53Ga0.47As Vertical Tunnel Transistor", Device Research Conference (DRC), Univ. of California, Santa Barbara, pp. 203-204, June 2011 [PDF]

[54] F. Li, Z. Fang, R. Misra, S. Tadigadapa, Q. Zhang and S. Datta, "Giant magnetoelectric effect in nanofabricated Pb(Zr0.52Ti0.48)O3-Fe85B5Si10 Cantilevers and resonant gate transistors", Device Research Conference (DRC), Univ. of California, Santa Barbara, pp. 237-238, pp. 69-70, June 2011 [PDF]

[53] L. Liu, V. Saripalli, V. Narayanan and S. Datta, "Experimental Investigation of Scalability and Transport in In0.7Ga0.3As Multi-Gate Quantum Well FET (MuQFET)", Device Research Conference (DRC), Univ. of California, Santa Barbara, pp. 17-18, June 2011[PDF]

[52] H. Madan, D. Veksler, Y.T. Chen, J. Huang, N. Goel, G. Bersuker and S. Datta, "Interface States at high-k/InGaAs interface: H2O vs. O3 based ALD Dielectric", Device Research Conference (DRC), Univ. of California, Santa Barbara, pp. 117-118, June 2011 [PDF]

[51] C. D. Young, M. Baykan, A. Agrawal, H. Madan, K. Akarvardar, C. Hobbs, I. OK, W. Taylor, C. E. Smith, M. M. Hussain, T. Nishida, S. Thompson, P. Majhi, P. Kirsch, S. Datta and R. Jammy, "Critical Discussion on (100) and (110) Orientation Dependent Transport : nMOS Planar and FinFET",?i> Intl. Symposium on VLSI Technology (VLSI), Kyoto, Japan, June, 2011. [PDF]

[50] L. Liu, V. Saripalli, E. Hwang, V. Narayanan and S. Datta, "Multi-Gate Modulation Doped In0.7Ga0.3As Quantum Well FET for Ultra Low Power Digital Logic", accepted for publication in 219th Electro chemical Society (ECS) Meeting, Montreal, Canada, May 1-6, 2011. [PDF]

[49] V. Saripalli, A. Misra, S. Datta and V. Narayanan, "An Energy-Efficient Heterogeneous CMP based on Hybrid TFET-CMOS Cores," Design Automation Conference (DAC), San Diego, June 5-10, 2011. [PDF]

[48] Y.C. Chen, S. Soumya, G. Sun, Y. Xie, S. Datta and V. Narayanan, "Automated Mapping for Reconfigurable Single Electron Transistor Arrays," Design Automation Conference (DAC) , San Diego, June 5-10, 2011. [PDF]

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2010

Journals

[35] A. Vallett, S. Minassian, P. Kaszuba, S. Datta, J. M. Redwing and T.S. Mayer, "Fabrication and Characterization of Axially Doped Silicon Nanowire Tunnel Field-Effect Transistors," NanoLetters, vol. 10, pp. 4813-4818, November 2010. [PDF]

[34] I. Geppert, M. Eizenberg, A. Ali and S. Datta, "Band offsets determination and interfacial chemical properties of the Al₂O₃/GaSb system," Applied Physics Letters, vol. 97, pp. 162109, October 2010. [PDF]

[33] W.C. Kao, A. Ali, E. Hwang, S. Mookerjea and S. Datta "Effect of interface states on sub-threshold response of III-V MOSFETs, MOS HEMTs and tunnel FETs", Solid-State Electronics, vol.54, pp. 16665-1668, August 2010. [PDF]

[32] A. Ali, H. S. Madan, A. P. Kirk, R. M. Wallace, D. A. Zhao, D. A. Mourey, M. K. Hudait, T. N. Jackson, B. R. Bennett, J. B. Boos, and S. Datta, "Fermi Level Unpinning of GaSb (100) using Plasma Enhanced Atomic Layer Deposition of Al2O3 Dielectric," Applied Physics Letters, vol. 97, pp. 143502, October 2010. [PDF]

[31] V. Saripalli, L. Liu, S. Datta and V. Narayanan, "Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits", Journal of Low Power Electronics, vol. 6, no. 3, pp. October 2010. [PDF]

[30] F. Li, F. Zhao, Q. M. Zhang and S. Datta, "Low-frequency voltage mode sensing of magnetoelectric sensor in package," Electronics Letters, vol. 46, no. 16, pp. August 2010. [PDF]

[29] S. Mookerjea, D. Mohata, T. Mayer, V. Narayanan, S. Datta, "Temperature-Dependent I-V Characteristics of a Vertical In_0.53Ga_0.47As Tunnel FET," IEEE Electron Device Letters, vol. 31, no. 6, pp. 564-567, June 2010. [PDF]

[28] A.Ali , H. Madan, S. Koveshnikov, S. Oktyabrsky, R. Kambhampati, T. Heeg, D. Schlom and S. Datta,"Small Signal Response of Inversion Layers in High Mobility In_0.53Ga_0.47As MOSFETs Made with Thin High-k Dielectrics," IEEE Transactions on Electron Devices vol. 57, no. 4, pp. 742-748, April 2010.[PDF]

[27] B. Downey, S. Datta and S. Mohney,"Numerical study of reduced contact resistance via nanoscale topography at metal/semiconductor interfaces," Semiconductor Science and Technology vol. 25, no. 1, pp 1-4, January 2010.[PDF]

[26] F. Li, S. H. Lee, Z. Fang, P. Majhi, Q. Zhang, S. K. Banerjee, and S. Datta, "Flicker Noise Improvement in 100 nm L_g Si_0.50Ge_0.50 Strained Quantum-Well Transistors using Ultra-Thin Si Cap Layer," IEEE Electron Device Letters, vol. 31, no. 1, pp. 47-49, January 2010.[PDF]

Conferences

[47] Z. Fang, F. Li, N. Mokhariwale, S. Datta, and Q. M. Zhang, "Direct integration of magnetoelectric sensors with microelectronics—Improved field sensitivity, signal-to-noise ratio and frequency response,", pp.15-16, IEEE Sensors 2010 Conference, pp. 614?19, Waikoloa, Hawaii, November 2010 [PDF]

[46] A. Ali, H. Madan, R. Misra, E.Hwang, A. Agrawal, P. Schiffer, J. B. Boos, B. R. Bennett, I. Geppert, M. Eizenberg and S. Datta,"Advanced Composite High-k Gate Stack for Mixed Anion Arsenide-Antimonide Quantum Well Transistors," IEEE International Electron Devices Meeting (IEDM 2010).[PDF]

[45] S. Datta, ,"Compound Semiconductor Based Tunnel Transistor Logic," Lester Eastman Conference on High Performance Devices (LEC 2010), pp.178-179, Troy, USA, August 2010 (Invited Talk)[PDF]

[44] S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer and V. Narayanan, "Non-silicon logic elements on silicon for extreme voltage scaling," Proceedings of the Silicon Nanoelectronics Workshop (SNW), pp.15-16, Honolulu, Hawaii, June 2010 (Invited Talk)[PDF]

[43] A. Ali, H. S. Madan, A. P. Kirk, R.M. Wallace, D. A. Zhao, D. A. Mourey, M. Hudait, T. N. Jackson, B. R. Bennett, J. B. Boos, and S. Datta,"Fermi Level Unpinning of GaSb(100) using Plasma Enhanced ALD Al₂O₃Dielectric," Device Research Conference Digest(DRC 2010) pp. 27-28, South Bend, Indiana, June 2010.[PDF]

[42] E. Hwang, S. Mookerjea, M. Hudait and S. Datta,"Scalability Study of In_0.70Ga_0.30As HEMTs for 22nm node and beyond Logic Applications ," Device Research Conference Digest(DRC 2010) pp. 61-62, South Bend, Indiana, June 2010.[PDF]

[41] A. Vallett, S. Minassian, S. Datta, J. Redwing and T. Mayer,"Fabrication of Axially-Doped Silicon Nanowire Tunnel FETs and Characterization of Tunneling Current," Device Research Conference Digest (DRC 2010) pp. 273-274, South Bend, Indiana, June 2010.[PDF]

[40] D. Pawlik, M. Barth, P. Thomas, S. Kurinec, S. Mookerjea, D. Mohata, S. Datta, S. Cohen, D. Ritter, S. Rommel,"Sub-Micron In_0.53Ga_0.47As Esaki Diodes With Record Current Density of 1MA/cm²," IEEE Device Research Conference Digest(DRC 2010) pp. 163-164, South Bend, Indiana, June 2010.[PDF]

[39] D. K. Mohata, D. Pawlik, L. Liu, S. Mookerjea, V. Saripalli, S. Rommel and S. Datta,"Implications of Record Peak Current Density In_0.53Ga_0.47As Esaki Tunnel Diode on Tunnel FET Logic Applications," Device Research Conference Digest (DRC 2010) pp. 101-102, South Bend, Indiana, June 2010.[PDF]

[38] L. Liu and S. Datta,"Investigation of the Scalability of Ultra Thin Body Double Gate Tunnel FET using Physics based 2D Analytical Model," IEEE Device Research Conference Digest (DRC 2010), pp. 103-104, South Bend, Indiana, June 2010.[PDF]

[37] V. Saripalli, D. K. Mohata, S. Mookerjea, S. Datta and V. Narayanan,"Low Power Loadless 4T SRAM cell based on Degenerately Doped Source (DDS) In_0.53Ga_0.47As Tunnel FETs," IEEE Device Research Conference Digest (DRC 2010) pp. 103-104, South Bend, Indiana, June 2010.[PDF]

[36] S. Datta, S. Mookerjea, D. Mohata, L. Liu, V. Saripalli, V. Narayanan and T. Mayer, "Compound Semiconductor Based Tunnel Transistor Logic," IEEE CS MANTECH Conference, pp. 203-204, Portland, Oregon, May 2010 (Invited talk by the candidate). [PDF]

[32] S. Datta, "III-V compound?MOSFET and TFET devices," Proceedings of the IEEE 11th Ultimate Integration of Silicon (ULIS) Conference, Glasgow, Scotland, March 2010 (Plenary Talk by the candidate).[PDF]

[35] J. Singh, R. Krishnan, S. Mookerjea, S. Datta, V. Narayanan,"A Novel Si TFET Based SRAM design for Ultra Low-Power 0.3V VDD Applications," Proceedings of 15th Asia Pacific Design Automation Conference (ASP-DAC 2010), Yokohama, Japan, January 2010.[PDF]

[34] V. Saripalli, V.,S. Datta and N. Vijaykrishnan,"Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors," International Conference on VLSI Design, India pp. 399-404, Bangalore, India, January 2010.[PDF]

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2009

Journals

[25] S. Mookerjea, R. Krishnan, S. Datta and V. Narayanan, "On Enhanced Miller Capacitance in Inter-Band Tunnel Transistors," IEEE Electron Device Letters, vol. 30, no. 10, pp. 1102-1104, October 2009.[PDF]

[24] A. Ali*, H. Madan*, S. Koveshnikov and S. Datta,” Small Signal Response of Inversion Layers in High Mobility In0.53Ga0.47As MOSFETs Made with Thin High-k Dielectrics”, Electrochemical Society (ECS) Transactions, Vol. 25, No. 6, pp. 271-284, Physics and Technology of High-k Gate Dielectrics, October 2009. (First and second authors supervised by the candidate)(Based on candidate’s invited talk)

[23] S. Mookerjea, R. Krishnan, S. Datta and V. Narayanan, "Effective Capacitance and Drive Current for Tunnel-FET (TFET) CV/I Estimation,"IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 2092-2098, September 2009 .[PDF]

[22] Z. Fang, S. G. Lu, F. Li, S. Datta and Q. M. Zhang, "Enhancing the Magnetoelectric Response of Metglas/Polyvinylidene fluoride Laminates by Exploiting the Flux Concentration Effect", Applied Physics Letters, 112903, September 2009.[PDF]

[21] S. Mookerjea*, R. Krishnan*, A. Vallett, T. Mayer and S. Datta, “Inter-band Tunnel Transistor Architecture using Narrow Gap Semiconductors”, ECS Transactions, Vol 19, No. 5, Ge and III-V MOSFETs, pp. 287-292, May 2009. (First author co-supervised and third author supervised by the candidate) (Based on Invited Talk by the candidate)

Conferences

[33] S. Mookerjea, D. Mohata, R. Krishnan, J. Singh, A. Vallett, A. Ali, T. Mayer, V. Narayanan, D. Schlom, A. Liu and S. Datta, "Experimental Demonstration of 100nm Channel Length In_0.53Ga_0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications" IEEE International Electron Devices Meeting (IEDM) Technical Digest, pp. 949-951, December, 2009.[PDF]

[32] Z. Fang, S. Lu, F. Li, N. Mokhariwale, S. Datta and Q.M. Zhang, "Sensitivity enhancement of magnetic sensors based on Metglas/PVDF laminates using the flux concentration effect," Nanoelectronic Devices for Defense and Security Conference (NANO DDS), September 2009.[PDF]

[31] S. Mookerjea and S. Datta, "Band-gap Engineered Hot Carrier Tunnel Transistors," 67^th Device Res. Conference (DRC), pp. 121-122, June 2009.[PDF]

[30] A. Ali, S. Mookerjea, E. Hwang, S. Koveshnikov, S. Oktyabrsky, V. Tokranov, M. Yakimov, R. Kambhampati, W. Tsai and S. Datta, "HfO₂ Gated, Self Aligned and Directly Contacted Indium Arsenide Quantum-well Transistors for Logic Applications - A Temperature and Bias Dependent Study," 67^th Device Research Conference (DRC), pp. 55-56, June 2009.[PDF]

[29] D. J. Pawlik, P. Thomas, M. Barth, K. Johnson, S.L. Rommel, S. Mookerjea , S. Datta, M. Luisier , G. Klimeck, Z.Cheng, J. Li, J.S. Park, J.M. Hydrick, J.G. Fiorenza, and A. Lochtefeld, "Indium Gallium Arsenide on Silicon Interband Tunnel Diodes for NDR-based memory and Steep Subthreshold Slope Transistor Applications," 67^th Device Research Conference (DRC), pp. 69-70, June 2009.

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2008

Journals

[20] D. Schlom, S. Guha and S. Datta, "Gate Oxides Beyond SiO2", MRS Bulletin, pp. 1017-1025, November 2008.

[19] S. H. Lee, P. Majhi, J. Oh, B. Sassman, C. Young, A. Bowonder, W. Y. Loh, J. J. Choi, B. J. Cho, H. D. Lee, P. Kirsch, H. R. Harris, W. Tsai, S. Datta, H. H. Tseng, S. K. Banerjee, and R. Jammy, "Demonstration of Lg 55 nm pMOSFETs With Si/ Si_0.25Ge_0.75/ Si Channels, High Ion Ioff (5x10⁴), and Controlled Short Channel Effects (SCEs)", IEEE Electron Device Letters, vol 29, No 9, 1017-1020 September 2008.

[18] C. I Kuo, H. T Hsu, E. Y. Chang, C. Y. Chang, Y. Miyamoto, S. Datta, M. Radosavljevic, G. W. Huang and C.T. Lee, "RF and Logic Performance Improvement of In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As Composite-Channel HEMT Using Gate-Sinking Technology", IEEE Electron Device Letters, vol. 29, no. 4, pp. 290-293, April 2008.

Conferences

[28] N. Goel, D. Heh, S. Koveshnikov, I. OK, S. Oktyabrsky, V. Tokranov, R. Kambhampati, M. Yakimov, Y. Sun, P. Pianetta, C. Gaspe, M. Santos, J. Lee, S. Datta, P. Majhi, and W. Tsai, "Addressing The Gate Stack Challenge For High Mobility In_xGa_1-xAs Channels For NFETs", International Electron Devices Meeting Technical Digest (IEDM) pp. 363-366, December, 2008.

[27] S. Datta, "Sub-Quarter Volt Supply Voltage III-V Tunnel Transistors for Green Nanoelectronics" 39th IEEE Semiconductor Interface Specialists Conference (SISC), December 2008 (Invited Talk).

[26] V. Saripalli, S. Mookerjea, S. Datta, and V. Narayanan, "Ultra low power signal processing architectures," IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 333 - 336, Nov. 2008.[PDF]

[25] S. Mookerjea and S. Datta, "Comparative Study of Si, Ge and InAs Based Steep Subthreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications," 66^th Device Research Conference (DRC), pp. 47-48, Jun. 2008.[PDF]

[24] S. Datta, "Compound Semiconductor as CMOS Channel Material - Deja vu or New Paradigm?" 66^th Device Research Conference (DRC), pp 33-36, June 2008 (Invited Talk).

[23] S. Eachempati, V. Saripalli, N. Vijaykrishnan and S. Datta, "Reconfigurable BDD Based Quantum Circuits," IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 61-67, June 2008.

[22] S. Datta, "Enabling Green Transistors with Narrow Bandgap Ccompound Semiconductors", 32^nd Workshop on Compound Semiconductor Devices and Integrated Circuits (WOCSDICE), May 2008 (Invited Talk).

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2007

Journals

[17] R. Chau, B. Doyle, S. Datta, K. Kavalieros and K. Zhang, "Integrated nanoelectronics for the future", Nature Materials, vol 6, pp. 810-812, November 2007.[PDF]

[16] S. Datta, G. Dewey, J. M. Fastenau, M. K. Hudait, D. Loubychev, W. K. Liu, M. Radosavljevic, W. Rachmady and R. Chau, "Ultrahigh-Speed 0.5 V Supply Voltage In_0.7Ga_0.3As Quantum-Well Transistors on Silicon Substrate", IEEE Electron Device Letters, vol. 28, no. 8, pp. 685-687, August 2007.[PDF]

[15] S. Datta, "III-V field-effect transistors for low power digital logic applications", Journal of Microelectronic Engineering, vol. 84 , no. 9-10, pp. 2133-2137, September 2007.[PDF]

[14] C. Y. Chang, H. T. Hsu, E. Y. Chang, C. I. Kuo, S. Datta, M. Radosavljevic, M. Miyamoto, G.W. Y. Huang "Investigation of Impact Ionization in InAs-Channel HEMT for High-Speed and Low-Power Applications", IEEE Electron Device Letters, vol. 28, no. 10, pp. 856-858, October 2007.

[13] T. Ashley, L. Buckle, S. Datta, M.T. Emeny, D.G. Hayes, K.P. Hilton, R. Jefferies, T. Martin, T.J. Phillips, D.J. Wallis, P.J. Wilding and R. Chau, "Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications", Electronics Letters, vol. 43 no. 14, July 2007.[PDF]

Conferences

[21] M. K. Hudait, S. Datta, G. Dewey, J. M. Fastenau, J. Kavalieros, W. K. Liu, D. Lubyshev, R. Pillarisetty, M. Radosavljevic and R. Chau, "Heterogeneous Integration of Enhancement Mode In_0.7Ga_0.3As Quantum Well Transistor on Silicon Substrate using Thin (<2 um) Composite Buffer Architecture for High-Speed and Low-voltage (0.5V) Logic Applications", International Electron Devices Meeting Technical Digest (IEDM), pp. 625-628, December 2007.[PDF]

[20] M. Chandhok, S. Datta, D. Lionberger, S. Vesecky "Impact of Line Width Roughness of Intel's 65 nm Process Devices", Proceedings of SPIE, pp. 6519, 2007.

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2006

Conferences

[19] J. Kavalieros, B. S. Doyle, S. Datta, G. Dewey and R. Chau "Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering," Digest of Technical Papers VLSI Technology Symposium, pp.62-63, June 2006.[PDF]

[18] S. Datta, "Antimonide based Quantum Well Transistors for High Speed, Low Power Logic Applications", Proceedings of the International Conference on Indium Phosphide and Related Materials (IPRM), Princeton, pp. 174 - 176, May 2006.

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2005

Journals

[12] R. Chau, S. Datta, M. Doczy, et al. "Benchmarking nanotechnology for high-performance and low-power logic transistor applications," IEEE Transactions on Nanotechnology, vol. 4, no. 2, pp. 153-158, March 2005.[PDF]

[11] R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic, "Application of high-K gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology," Journal of Microelectronic Engineering, vol. 80, no. 17, pp. 1-6, June 2005.[PDF]

Conferences

[16] S. Datta, T. Ashley, J. Brask, L. Buckle, M. Doczy, M. Emeny, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. Phillips, D. Wallis, P. Wilding, R. Chau, "85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications", International Electron Devices Meeting (IEDM) Technical Digest, pp. 763-766, Dec 2005.[PDF]

[16] R. Chau, S. Datta and A. Majumdar, "Opportunities and Challenges of III-V Nanoelectronics for Future High-speed, Low-power Logic Applications," Technical Digest, IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), pp. 17-20, Nov. 2005.[PDF]

[15] S. Datta, "Silicon and III-V nanoelectronics", Proceedings of the International Conference on Indium Phosphide and Related Materials (IPRM), Glasgow, Scotland, pp. 7 - 8, May 2005

[14] R. Chau, J. Brask, S. Datta, G. Dewey, M. Doczy, B. Doyle, J. Kavalieros, B. Jin, M. Metz, A. Majumdar and M. Radosavljevic, "Emerging Silicon and Non-Silicon Nano-electronic Devices: Opportunities and Challenges for Future High-Performance and Low-Power Computational Applications," Proceedings of Technical Papers, IEEE VLSI-TSA International Symposium on VLSI Technology (VLSI TSA), Hsinchu, Taiwan, pp. 13-16, April 2005.

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2004

Journals

[10] R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and M. Metz, "High-K/Metal-Gate Stack and Its MOSFET Characteristics," IEEE Electron Device Letters, vol. 25, no. 6, pp. 408-410, June 2004.[PDF]

Conferences

[13] S. Datta, T. Ashley, A. Barnes, L. Buckle, A. Dean, M. Emeny, M. Fearn, D. Hayes, K. Hilton, R. Jefferies, T. Martin, K. Nash, T. Philips, W. Tang, P. Wilding and R. Chau, "Novel InSb-based Quantum Well Transistors for Ultra-High Speed, Low Power Logic Applications," Proceedings 7th International Conference on Solid-State and Integrated Circuits Technology (ICSICT), pp. 2253-2256, Beijing, China, Oct. 2004

[12] B. Jin, S. Datta, G. Dewey, M. Doczy, B. Doyle, K. Johnson, J. Kavalieros, M. Metz, U. Shah, N. Zelick and R. Chau, "Mobility Enhancement in Compressively Strained SiGe Surface Channel pMOS(FET) with HfO₂/TiN Gate Stack," Proceedings of the ECS 2004 Joint International Meeting, SiGe: Materials Processing and Devices, pp. 111-122, Oct. 2004

[11] S. Datta, "Advanced Si and SiGe Strained NMOS and PMOS Transistors with High-K/Metal-Gate Stack," Proceedings of the Bipolar/BiCMOS Circuits and Technology Meetings (BCTM), Montreal, Canada, pp. 194-197, Sept. 2004.[PDF]

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2003

Journals

[9] R. Chau, B. Boyanov, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros, and M. Metz, "Silicon Nano-transistors for Logic Applications," PHYSICA E, Low-Dimensional Systems and Nanostructures, Vol. 19, Issues 1-2, pp.1-5, July 2003.[PDF]

[8] B.S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High Performance Fully-Depleted Tri-Gate CMOS Transistors," IEEE Electron Device Letters, Vol. 24, No. 4, pp.263-265, April 2003.[PDF]

Conferences

[10] S. Datta, G. Dewey, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, M. Metz, N. Zelick and R. Chau, "High mobility Si/SiGe strained channel MOS transistors with HfO2/TiN gate stacks", International Electron Devices Meeting (IEDM) Technical Digest, pp. 28.1.1 - 28.1.4, December 2003. [PDF]

[9] R. Chau, S. Datta, M. Doczy, J. Kavalieros and M. Metz, "Gate Dielectric Scaling for High-Performance CMOS: from SiO2 to High-K," Extended Abstracts of International Workshop on Gate Insulator (IWGI), Tokyo, Japan, pp.124-126, Nov. 2003.

[8] R. Chau, B. Doyle, M. Doczy, S. Datta, S. Hareland, B. Jin, J. Kavalieros and M. Metz, "Silicon Nano-Transistors and Breaking the 10nm Physical Gate Length Barrier," 61^st Device Research Conference (DRC), pp.123-126, June 2003. [PDF]

[7] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, “Tri-Gate Fully-Depleted CMOS Transistors: Fabrication, Design and Layout,” Digest of Technical Papers VLSI Technology Symposium, pp. 133-134, Kyoto, Japan, June 10-12, 2003. (Equal contribution by all authors)

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2002

Conferences

[6] R. Chau, B. Doyle, J. Kavalieros, D. Barlage, A. Murthy, M. Doczy, R. Arghavani, and S. Datta, "Advanced Depleted-Substrate Transistors: Single-gate, Double-Gate and Tri-gate," Extended Abstracts of the International Conference on Solid-State Devices and Materials (SSDM), pp. 68-69, 2002.

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2000

Journals

[7] S. Datta, K. P. Roenker, M. M. Cahay and L. M. Lunardi , " Analytical Modeling of Pnp InP/InGaAs Heterojunction Bipolar Transistors," Solid State Electronics , vol. 44, no. 7, pp. 1331-1333, July 2000 .

[6] S. Datta, K. P. Roenker and M. M. Cahay, "A Gummel-Poon Model for Pnp Heterojunction Bipolar Transistors with a Compositionally Graded Base," Solid-State Electronics, vol. 44, no. 6, pp. 991-1000, June 2000.

Conferences

[5] S. Datta, K. P. Roenker, R. E. Peddenpohl II and M. M. Cahay, "Analysis of High Current Effects on the Performance of Pnp InP-Based Heterojunction Bipolar Transistors," Proceedings of Twelfth International Conference on InP and Related Materials (IPRM), pp. 134-137, May 2000.

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1999

Journals

[5] S. Datta, K. P. Roenker and M. M. Cahay , " Emitter Series Resistance Effect of Multiple Heterojunction Contacts for Pnp Heterojunction Bipolar Transistors," Solid-State Electronics , vol. 43, no. 7, pp. 1299-1305, 1999 .

[4] S. Datta, K. P. Roenker and M. M. Cahay , " Hole Transport and Quasi-Fermi Level Splitting at the Emitter-Base Junction in Pnp Heterojunction Bipolar Transistors," Journal of Applied Physics , vol. 85, no. 3, pp. 1949-1955, Feb 1999 .

[3] S. Datta, K. P. Roenker and M. M. Cahay , " Implications of Hole versus Electron Transport Properties for High Speed Pnp Heterojunction Bipolar Transistors," Solid-State Electronics , vol. 43, no. 1, pp. 73-80, Jan 1999 .

Conferences

[4] S. Datta, K. P. Roenker, and M. M. Cahay , " Base Pushout and High Current Effects in InP-Based Pnp Heterojunction Bipolar Transistors,"Proceedings of the State-of-the-Art Program on Compound Semiconductors , Electrochemical Society, vol.99-17, Oct. 1999.

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1998

Journals

[2] S. Datta, S. Shi, K. P. Roenker and M. M. Cahay and W. E. Stanchina , " Simulation and Design of InAlAs/InGaAs Pnp Heterojunction Bipolar Transistors ," IEEE Transactions on Electron Devices , vol. 45, no. 8, pp. 1634-1643, Aug. 1998 .

[1] S. Datta, K. P. Roenker and M. M. Cahay , " A Thermionic-Emission-Diffusion Model for a Graded Base Pnp Heterojunction Bipolar Transistors,"Journal of Applied Physics , vol. 83, no. 12, pp. 8036-8045, June 1998.

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Conferences

[3] S. Datta, K. P. Roenker and M. M. Cahay , " High Current and Two Dimensional Effects in InP-Based Pnp Heterojunction Bipolar Transistors ,"Proceedings of the State-of-the-Art Program on Compound Semiconductors , , Electrochemical Society, vol. 98-12, 1998 .

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1997

Conferences

[2] S. Datta, S. Shi, K. P. Roenker and M. M. Cahay , " Base Design for Pnp InAlAs/InGaAs Heterojunction Bipolar Transistors," Proceedings of the State-of-the-Art Program on Compound Semiconductors, Electrochemical Society, vol. 97-1, pp. 272-287, 1997 .

[1] S. Datta, S. Shi, K. P. Roenker, M. M. Cahay and W. E. Stanchina , " Numerical Modeling and Design of Pnp InAlAs-InGaAs Heterojunction Bipolar Transistors," Proceedings of the Ninth International Conference on InP and Related Materials (IPRM) , pp. 392-395, 1997.

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