Matthew San Jose

Doctoral Student

Photo of Matthew San Jose
131 Stinson Remick Hall


Matthew San Jose received his B.S. in Nanoscale Engineering from the SUNY Polytechnic Institute in 2019, and his M.S. in Electrical Engineering from the University of Notre Dame in 2021. His research interests include the gate oxide thickness scaling of Si MOSFETs, by using novel CMOS-compatible high-k dielectrics in fabricated devices.


1. W. Chakraborty, M.S. Jose, J. Gomez, A.Saha, K.A. Aabrar, P. Fay, S. Gupta and S. Datta, “Higher-k Zirconium Doped Hafnium Oxide ( HZO ) Trigate Transistors with Higher DC and RF Performance and Improved Reliability,” 2021 Symp. VLSI Technol., vol. 47907, pp. T7-1, 2021.

2. S. Dutta, H. Ye , W. Chakraborty, Y.-C. Luo, M. San Jose, B. Grisafe, A. Khanna, I. Lightcap, S. Shinde, S. Yu and S. Datta, “Monolithic 3D Integration of High Endurance Multi-Bit Ferroelectric FET for Accelerating Compute-In-Memory,” 2020 IEEE Int. Electron Devices Meet., vol. 1, no. c, pp. 801–804, 2020.

3. S. Dutta, B. Grisafe, C. Frentzel, Z. Encisco, M. San Jose, J. Smith, K. Ni, S. Joshi, S. Datta, “Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security,” IEEE Trans. Electron Devices, vol. 68, no. 2, pp. 516–522, 2021.


Schmitt Fellowship.

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