Jeffrey Smith

Doctoral Student

Photo of Jeffrey Smith
Office
131 Stinson-Remick Hall
Phone
574-631-1290
Email
jsmith80@nd.edu

Bio

Jeff graduated with dual degrees in Physics and Mathematics from Clarkson University in May 2015, where he developed compact thermal circuit models for multiple gate SOI FETs. He completed the M.S. in Electrical Engineering in 2017 and expects to complete the Ph.D. degree in 2020. His research interests include semiconductor device modeling of low power transistors, investigation of novel semiconductors for transistor application and reliability analysis of emerging devices.

Research Interests

  • Integration of novel materials and conventional devices for low power, high performance transistors
  • Mitigation of intrinsic device reliability and variation through novel semiconductor process techniques
  • Physics-based TCAD modeling of advanced Silicon and non-Silicon 3D transistor architectures

Publications

[1] J.A. Smith, M. Barth, K. Ni, M. Cantoro, D.-W. Kim, S. Datta, “Corrugated channel In0.8Ga0.2As quantum well transistors for low power logic applications”, 75thl Device Research Conference, Notre Dame, 2017.

[2] Jeffrey A. Smith, Kai Ni, Ram Krishna Ghosh, Jeff Xu, Mustafa Badaroglu, PR Chidi Chidambaram, and Suman Datta, "Investigation of electrically gate-all-around hexagonal nanowire FET (HexFET) architecture for 5 nm node logic and SRAM applications," 47th European Solid-State Device Research Conference (ESSDERC), Leuven, 2017, pp. 188-191.

[3] Mustafa Badaroglu, Jeff Xu, John Zhu, Da Yang, Jerry Bao, Seung-Chul Song, Peijie Feng, Romain Ritzenthaler, Hans Mertens, Geert Eneman, Naoto Horiguchi, Jeffrey Smith, Suman Datta, David Kohen, Po-Wen Chan, Keagan Chen, and PR Chidi Chidambaram, "PPAC scaling enablement for 5nm mobile SoC technology," 47th European Solid-State Device Research Conference, Leuven, 2017, pp. 240-243.

[4] J.A. Smith, H. Takeuchi, R. Stephenson, Y.A. Chen, M. Hytha, R. J. Mears, and S. Datta, “Experimental Investigation of N-Channel Oxygen-Inserted (OI) Silicon Channel MOSFETs with High-K/Metal Gate Stack,” 76th Device Research Conference, Santa Barbara, 2018.

Honors

  • Dean’s Fellowship, University of Notre Dame, March 2015
  • Honorable Mention, Barry M. Goldwater Scholarship, March 2014

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